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Sanjay R Mehtavinodkoul
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dmaengine: ptdma: register PTDMA controller as a DMA resource
Register ptdma queue to Linux dmaengine framework as general-purpose DMA channels. Signed-off-by: Sanjay R Mehta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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drivers/dma/ptdma/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
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config AMD_PTDMA
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tristate "AMD PassThru DMA Engine"
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depends on X86_64 && PCI
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
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Enable support for the AMD PTDMA controller. This controller
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provides DMA capabilities to perform high bandwidth memory to

drivers/dma/ptdma/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,6 @@
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obj-$(CONFIG_AMD_PTDMA) += ptdma.o
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8-
ptdma-objs := ptdma-dev.o
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ptdma-objs := ptdma-dev.o ptdma-dmaengine.o
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ptdma-$(CONFIG_PCI) += ptdma-pci.o

drivers/dma/ptdma/ptdma-dev.c

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,26 @@ static inline void pt_core_enable_queue_interrupts(struct pt_device *pt)
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iowrite32(SUPPORTED_INTERRUPTS, pt->cmd_q.reg_control + 0x000C);
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}
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static void pt_do_cmd_complete(unsigned long data)
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{
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struct pt_tasklet_data *tdata = (struct pt_tasklet_data *)data;
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struct pt_cmd *cmd = tdata->cmd;
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struct pt_cmd_queue *cmd_q = &cmd->pt->cmd_q;
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u32 tail;
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if (cmd_q->cmd_error) {
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/*
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* Log the error and flush the queue by
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* moving the head pointer
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*/
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tail = lower_32_bits(cmd_q->qdma_tail + cmd_q->qidx * Q_DESC_SIZE);
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pt_log_error(cmd_q->pt, cmd_q->cmd_error);
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iowrite32(tail, cmd_q->reg_control + 0x0008);
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}
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cmd->pt_cmd_callback(cmd->data, cmd->ret);
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}
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static irqreturn_t pt_core_irq_handler(int irq, void *data)
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{
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struct pt_device *pt = data;
@@ -143,6 +163,7 @@ static irqreturn_t pt_core_irq_handler(int irq, void *data)
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/* Acknowledge the interrupt */
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iowrite32(status, cmd_q->reg_control + 0x0010);
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pt_core_enable_queue_interrupts(pt);
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pt_do_cmd_complete((ulong)&pt->tdata);
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}
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return IRQ_HANDLED;
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}
@@ -224,8 +245,16 @@ int pt_core_init(struct pt_device *pt)
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pt_core_enable_queue_interrupts(pt);
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/* Register the DMA engine support */
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ret = pt_dmaengine_register(pt);
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if (ret)
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goto e_dmaengine;
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return 0;
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e_dmaengine:
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free_irq(pt->pt_irq, pt);
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e_dma_alloc:
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dma_free_coherent(dev, cmd_q->qsize, cmd_q->qbase, cmd_q->qbase_dma);
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@@ -242,6 +271,9 @@ void pt_core_destroy(struct pt_device *pt)
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struct pt_cmd_queue *cmd_q = &pt->cmd_q;
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struct pt_cmd *cmd;
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/* Unregister the DMA engine */
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pt_dmaengine_unregister(pt);
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/* Disable and clear interrupts */
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pt_core_disable_queue_interrupts(pt);
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