Skip to content

Commit c739271

Browse files
ideakideak
committed
drm/i915/tgl+: Sanitize the DDI LANES/IO and AUX power domain names
In Bspec the TGL TypeC ports are TC1-6, the AUX power well request flags are USBC1-6/TBT1-6, so for clarity use these names in the port power domain names instead of the D-I terminology (which Bspec uses only for the ICL TypeC ports). A domain name should follow the <domain>_<pipe/transcoder/port/aux_ch> format. Add the new aliases based on this, leaving a change to rename all the rest accordingly for a follow-up. No functional change. v2: Add comment to commit log about unifying domain names. (Jose) Cc: Souza Jose <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
1 parent 62c211b commit c739271

File tree

2 files changed

+130
-114
lines changed

2 files changed

+130
-114
lines changed

‎drivers/gpu/drm/i915/display/intel_display_power.c

Lines changed: 98 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -2886,24 +2886,24 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
28862886
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
28872887
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
28882888
BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
2889-
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
2890-
BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
2891-
BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
2892-
BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) | \
2893-
BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) | \
2894-
BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) | \
2895-
BIT_ULL(POWER_DOMAIN_AUX_D) | \
2896-
BIT_ULL(POWER_DOMAIN_AUX_E) | \
2897-
BIT_ULL(POWER_DOMAIN_AUX_F) | \
2898-
BIT_ULL(POWER_DOMAIN_AUX_G) | \
2899-
BIT_ULL(POWER_DOMAIN_AUX_H) | \
2900-
BIT_ULL(POWER_DOMAIN_AUX_I) | \
2901-
BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
2902-
BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
2903-
BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
2904-
BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
2905-
BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
2906-
BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
2889+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
2890+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
2891+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
2892+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
2893+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
2894+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
2895+
BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
2896+
BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
2897+
BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
2898+
BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
2899+
BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
2900+
BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
2901+
BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
2902+
BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
2903+
BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
2904+
BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
2905+
BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
2906+
BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
29072907
BIT_ULL(POWER_DOMAIN_VGA) | \
29082908
BIT_ULL(POWER_DOMAIN_AUDIO) | \
29092909
BIT_ULL(POWER_DOMAIN_INIT))
@@ -2921,18 +2921,12 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
29212921
BIT_ULL(POWER_DOMAIN_AUX_C) | \
29222922
BIT_ULL(POWER_DOMAIN_INIT))
29232923

2924-
#define TGL_DDI_IO_D_TC1_POWER_DOMAINS ( \
2925-
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
2926-
#define TGL_DDI_IO_E_TC2_POWER_DOMAINS ( \
2927-
BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
2928-
#define TGL_DDI_IO_F_TC3_POWER_DOMAINS ( \
2929-
BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
2930-
#define TGL_DDI_IO_G_TC4_POWER_DOMAINS ( \
2931-
BIT_ULL(POWER_DOMAIN_PORT_DDI_G_IO))
2932-
#define TGL_DDI_IO_H_TC5_POWER_DOMAINS ( \
2933-
BIT_ULL(POWER_DOMAIN_PORT_DDI_H_IO))
2934-
#define TGL_DDI_IO_I_TC6_POWER_DOMAINS ( \
2935-
BIT_ULL(POWER_DOMAIN_PORT_DDI_I_IO))
2924+
#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
2925+
#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
2926+
#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
2927+
#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
2928+
#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
2929+
#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
29362930

29372931
#define TGL_AUX_A_IO_POWER_DOMAINS ( \
29382932
BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
@@ -2941,44 +2935,34 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
29412935
BIT_ULL(POWER_DOMAIN_AUX_B))
29422936
#define TGL_AUX_C_IO_POWER_DOMAINS ( \
29432937
BIT_ULL(POWER_DOMAIN_AUX_C))
2944-
#define TGL_AUX_D_TC1_IO_POWER_DOMAINS ( \
2945-
BIT_ULL(POWER_DOMAIN_AUX_D))
2946-
#define TGL_AUX_E_TC2_IO_POWER_DOMAINS ( \
2947-
BIT_ULL(POWER_DOMAIN_AUX_E))
2948-
#define TGL_AUX_F_TC3_IO_POWER_DOMAINS ( \
2949-
BIT_ULL(POWER_DOMAIN_AUX_F))
2950-
#define TGL_AUX_G_TC4_IO_POWER_DOMAINS ( \
2951-
BIT_ULL(POWER_DOMAIN_AUX_G))
2952-
#define TGL_AUX_H_TC5_IO_POWER_DOMAINS ( \
2953-
BIT_ULL(POWER_DOMAIN_AUX_H))
2954-
#define TGL_AUX_I_TC6_IO_POWER_DOMAINS ( \
2955-
BIT_ULL(POWER_DOMAIN_AUX_I))
2956-
#define TGL_AUX_D_TBT1_IO_POWER_DOMAINS ( \
2957-
BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
2958-
#define TGL_AUX_E_TBT2_IO_POWER_DOMAINS ( \
2959-
BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
2960-
#define TGL_AUX_F_TBT3_IO_POWER_DOMAINS ( \
2961-
BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
2962-
#define TGL_AUX_G_TBT4_IO_POWER_DOMAINS ( \
2963-
BIT_ULL(POWER_DOMAIN_AUX_G_TBT))
2964-
#define TGL_AUX_H_TBT5_IO_POWER_DOMAINS ( \
2965-
BIT_ULL(POWER_DOMAIN_AUX_H_TBT))
2966-
#define TGL_AUX_I_TBT6_IO_POWER_DOMAINS ( \
2967-
BIT_ULL(POWER_DOMAIN_AUX_I_TBT))
2938+
2939+
#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
2940+
#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
2941+
#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
2942+
#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
2943+
#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
2944+
#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
2945+
2946+
#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
2947+
#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
2948+
#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
2949+
#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
2950+
#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
2951+
#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
29682952

29692953
#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
2970-
BIT_ULL(POWER_DOMAIN_AUX_D) | \
2971-
BIT_ULL(POWER_DOMAIN_AUX_E) | \
2972-
BIT_ULL(POWER_DOMAIN_AUX_F) | \
2973-
BIT_ULL(POWER_DOMAIN_AUX_G) | \
2974-
BIT_ULL(POWER_DOMAIN_AUX_H) | \
2975-
BIT_ULL(POWER_DOMAIN_AUX_I) | \
2976-
BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
2977-
BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
2978-
BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
2979-
BIT_ULL(POWER_DOMAIN_AUX_G_TBT) | \
2980-
BIT_ULL(POWER_DOMAIN_AUX_H_TBT) | \
2981-
BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \
2954+
BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
2955+
BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
2956+
BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
2957+
BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
2958+
BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
2959+
BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
2960+
BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
2961+
BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
2962+
BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
2963+
BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
2964+
BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
2965+
BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
29822966
BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
29832967

29842968
#define RKL_PW_4_POWER_DOMAINS ( \
@@ -2994,10 +2978,10 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
29942978
BIT_ULL(POWER_DOMAIN_AUDIO) | \
29952979
BIT_ULL(POWER_DOMAIN_VGA) | \
29962980
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
2997-
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
2998-
BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
2999-
BIT_ULL(POWER_DOMAIN_AUX_D) | \
3000-
BIT_ULL(POWER_DOMAIN_AUX_E) | \
2981+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
2982+
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
2983+
BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
2984+
BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
30012985
BIT_ULL(POWER_DOMAIN_INIT))
30022986

30032987
/*
@@ -4145,8 +4129,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41454129
}
41464130
},
41474131
{
4148-
.name = "DDI D TC1 IO",
4149-
.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
4132+
.name = "DDI IO TC1",
4133+
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
41504134
.ops = &hsw_power_well_ops,
41514135
.id = DISP_PW_ID_NONE,
41524136
{
@@ -4155,8 +4139,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41554139
},
41564140
},
41574141
{
4158-
.name = "DDI E TC2 IO",
4159-
.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
4142+
.name = "DDI IO TC2",
4143+
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
41604144
.ops = &hsw_power_well_ops,
41614145
.id = DISP_PW_ID_NONE,
41624146
{
@@ -4165,8 +4149,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41654149
},
41664150
},
41674151
{
4168-
.name = "DDI F TC3 IO",
4169-
.domains = TGL_DDI_IO_F_TC3_POWER_DOMAINS,
4152+
.name = "DDI IO TC3",
4153+
.domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
41704154
.ops = &hsw_power_well_ops,
41714155
.id = DISP_PW_ID_NONE,
41724156
{
@@ -4175,8 +4159,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41754159
},
41764160
},
41774161
{
4178-
.name = "DDI G TC4 IO",
4179-
.domains = TGL_DDI_IO_G_TC4_POWER_DOMAINS,
4162+
.name = "DDI IO TC4",
4163+
.domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
41804164
.ops = &hsw_power_well_ops,
41814165
.id = DISP_PW_ID_NONE,
41824166
{
@@ -4185,8 +4169,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41854169
},
41864170
},
41874171
{
4188-
.name = "DDI H TC5 IO",
4189-
.domains = TGL_DDI_IO_H_TC5_POWER_DOMAINS,
4172+
.name = "DDI IO TC5",
4173+
.domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
41904174
.ops = &hsw_power_well_ops,
41914175
.id = DISP_PW_ID_NONE,
41924176
{
@@ -4195,8 +4179,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41954179
},
41964180
},
41974181
{
4198-
.name = "DDI I TC6 IO",
4199-
.domains = TGL_DDI_IO_I_TC6_POWER_DOMAINS,
4182+
.name = "DDI IO TC6",
4183+
.domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
42004184
.ops = &hsw_power_well_ops,
42014185
.id = DISP_PW_ID_NONE,
42024186
{
@@ -4241,8 +4225,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
42414225
},
42424226
},
42434227
{
4244-
.name = "AUX D TC1",
4245-
.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
4228+
.name = "AUX USBC1",
4229+
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
42464230
.ops = &icl_aux_power_well_ops,
42474231
.id = DISP_PW_ID_NONE,
42484232
{
@@ -4252,8 +4236,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
42524236
},
42534237
},
42544238
{
4255-
.name = "AUX E TC2",
4256-
.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
4239+
.name = "AUX USBC2",
4240+
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
42574241
.ops = &icl_aux_power_well_ops,
42584242
.id = DISP_PW_ID_NONE,
42594243
{
@@ -4263,8 +4247,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
42634247
},
42644248
},
42654249
{
4266-
.name = "AUX F TC3",
4267-
.domains = TGL_AUX_F_TC3_IO_POWER_DOMAINS,
4250+
.name = "AUX USBC3",
4251+
.domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
42684252
.ops = &icl_aux_power_well_ops,
42694253
.id = DISP_PW_ID_NONE,
42704254
{
@@ -4274,8 +4258,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
42744258
},
42754259
},
42764260
{
4277-
.name = "AUX G TC4",
4278-
.domains = TGL_AUX_G_TC4_IO_POWER_DOMAINS,
4261+
.name = "AUX USBC4",
4262+
.domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
42794263
.ops = &icl_aux_power_well_ops,
42804264
.id = DISP_PW_ID_NONE,
42814265
{
@@ -4285,8 +4269,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
42854269
},
42864270
},
42874271
{
4288-
.name = "AUX H TC5",
4289-
.domains = TGL_AUX_H_TC5_IO_POWER_DOMAINS,
4272+
.name = "AUX USBC5",
4273+
.domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
42904274
.ops = &icl_aux_power_well_ops,
42914275
.id = DISP_PW_ID_NONE,
42924276
{
@@ -4296,8 +4280,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
42964280
},
42974281
},
42984282
{
4299-
.name = "AUX I TC6",
4300-
.domains = TGL_AUX_I_TC6_IO_POWER_DOMAINS,
4283+
.name = "AUX USBC6",
4284+
.domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
43014285
.ops = &icl_aux_power_well_ops,
43024286
.id = DISP_PW_ID_NONE,
43034287
{
@@ -4307,8 +4291,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
43074291
},
43084292
},
43094293
{
4310-
.name = "AUX D TBT1",
4311-
.domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
4294+
.name = "AUX TBT1",
4295+
.domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
43124296
.ops = &icl_aux_power_well_ops,
43134297
.id = DISP_PW_ID_NONE,
43144298
{
@@ -4318,8 +4302,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
43184302
},
43194303
},
43204304
{
4321-
.name = "AUX E TBT2",
4322-
.domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
4305+
.name = "AUX TBT2",
4306+
.domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
43234307
.ops = &icl_aux_power_well_ops,
43244308
.id = DISP_PW_ID_NONE,
43254309
{
@@ -4329,8 +4313,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
43294313
},
43304314
},
43314315
{
4332-
.name = "AUX F TBT3",
4333-
.domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
4316+
.name = "AUX TBT3",
4317+
.domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
43344318
.ops = &icl_aux_power_well_ops,
43354319
.id = DISP_PW_ID_NONE,
43364320
{
@@ -4340,8 +4324,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
43404324
},
43414325
},
43424326
{
4343-
.name = "AUX G TBT4",
4344-
.domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
4327+
.name = "AUX TBT4",
4328+
.domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
43454329
.ops = &icl_aux_power_well_ops,
43464330
.id = DISP_PW_ID_NONE,
43474331
{
@@ -4351,8 +4335,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
43514335
},
43524336
},
43534337
{
4354-
.name = "AUX H TBT5",
4355-
.domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
4338+
.name = "AUX TBT5",
4339+
.domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
43564340
.ops = &icl_aux_power_well_ops,
43574341
.id = DISP_PW_ID_NONE,
43584342
{
@@ -4362,8 +4346,8 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
43624346
},
43634347
},
43644348
{
4365-
.name = "AUX I TBT6",
4366-
.domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
4349+
.name = "AUX TBT6",
4350+
.domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
43674351
.ops = &icl_aux_power_well_ops,
43684352
.id = DISP_PW_ID_NONE,
43694353
{
@@ -4471,8 +4455,8 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
44714455
}
44724456
},
44734457
{
4474-
.name = "DDI D TC1 IO",
4475-
.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
4458+
.name = "DDI IO TC1",
4459+
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
44764460
.ops = &hsw_power_well_ops,
44774461
.id = DISP_PW_ID_NONE,
44784462
{
@@ -4481,8 +4465,8 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
44814465
},
44824466
},
44834467
{
4484-
.name = "DDI E TC2 IO",
4485-
.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
4468+
.name = "DDI IO TC2",
4469+
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
44864470
.ops = &hsw_power_well_ops,
44874471
.id = DISP_PW_ID_NONE,
44884472
{
@@ -4511,8 +4495,8 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
45114495
},
45124496
},
45134497
{
4514-
.name = "AUX D TC1",
4515-
.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
4498+
.name = "AUX USBC1",
4499+
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
45164500
.ops = &icl_aux_power_well_ops,
45174501
.id = DISP_PW_ID_NONE,
45184502
{
@@ -4521,8 +4505,8 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
45214505
},
45224506
},
45234507
{
4524-
.name = "AUX E TC2",
4525-
.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
4508+
.name = "AUX USBC2",
4509+
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
45264510
.ops = &icl_aux_power_well_ops,
45274511
.id = DISP_PW_ID_NONE,
45284512
{

0 commit comments

Comments
 (0)