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[AMDGPU][GlobalISel] Add RegBankLegalize support for G_ASSERT_{S|Z}EXT ops (llvm#162728)
1 parent 5391c68 commit de67a78

10 files changed

+290
-46
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -633,6 +633,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
633633
.Any({{UniS64, S64}, {{Sgpr64}, {Sgpr64}}})
634634
.Any({{DivS64, S64}, {{Vgpr64}, {Vgpr64}, SplitTo32SExtInReg}});
635635

636+
addRulesForGOpcs({G_ASSERT_ZEXT, G_ASSERT_SEXT}, Standard)
637+
.Uni(S32, {{Sgpr32}, {Sgpr32, Imm}})
638+
.Div(S32, {{Vgpr32}, {Vgpr32, Imm}})
639+
.Uni(S64, {{Sgpr64}, {Sgpr64, Imm}})
640+
.Div(S64, {{Vgpr64}, {Vgpr64, Imm}});
641+
636642
bool hasSMRDx3 = ST->hasScalarDwordx3Loads();
637643
bool hasSMRDSmall = ST->hasScalarSubwordLoads();
638644
bool usesTrue16 = ST->useRealTrue16Insts();

‎llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -stop-after=irtranslator -o - %s | FileCheck %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji -stop-after=irtranslator -o - %s | FileCheck %s
33

44
declare align(8) dereferenceable(8) ptr @declared_with_ret_deref() #0
55
declare align(8) ptr @unknown_decl() #0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,15 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel -mattr=-promote-alloca -mattr=+enable-flat-scratch < %s | FileCheck -check-prefix=GFX9 %s
3-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -global-isel -mattr=-promote-alloca -mattr=+enable-flat-scratch < %s | FileCheck -check-prefix=GFX10 %s
4-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -global-isel -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX942 %s
5-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -global-isel -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX11 %s
6-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX12 %s
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel -new-reg-bank-select -mattr=-promote-alloca -mattr=+enable-flat-scratch < %s | FileCheck -check-prefix=GFX9 %s
3+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -global-isel -new-reg-bank-select -mattr=-promote-alloca -mattr=+enable-flat-scratch < %s | FileCheck -check-prefix=GFX10 %s
4+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -global-isel -new-reg-bank-select -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX942 %s
5+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -global-isel -new-reg-bank-select -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX11 %s
6+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel -new-reg-bank-select -mattr=-promote-alloca < %s | FileCheck -check-prefix=GFX12 %s
77

8-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel -mattr=-unaligned-access-mode -mattr=-promote-alloca -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX9 %s
9-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -global-isel -mattr=-unaligned-access-mode -mattr=-promote-alloca -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX10 %s
10-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -global-isel -mattr=-unaligned-access-mode -mattr=-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX942 %s
11-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -global-isel -mattr=-unaligned-access-mode -mattr=-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX11 %s
12-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel -mattr=-unaligned-access-mode -mattr=-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX12 %s
8+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -global-isel -new-reg-bank-select -mattr=-unaligned-access-mode -mattr=-promote-alloca -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX9 %s
9+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -global-isel -new-reg-bank-select -mattr=-unaligned-access-mode -mattr=-promote-alloca -mattr=+enable-flat-scratch < %s | FileCheck -check-prefixes=UNALIGNED_GFX10 %s
10+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -global-isel -new-reg-bank-select -mattr=-unaligned-access-mode -mattr=-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX942 %s
11+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -global-isel -new-reg-bank-select -mattr=-unaligned-access-mode -mattr=-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX11 %s
12+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel -new-reg-bank-select -mattr=-unaligned-access-mode -mattr=-promote-alloca < %s | FileCheck -check-prefixes=UNALIGNED_GFX12 %s
1313

1414
define amdgpu_kernel void @store_load_sindex_kernel(i32 %idx) {
1515
; GFX9-LABEL: store_load_sindex_kernel:

‎llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
3-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
4-
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
55

66
define amdgpu_kernel void @v_insert_v64i32_37(ptr addrspace(1) %ptr.in, ptr addrspace(1) %ptr.out) #0 {
77
; GCN-LABEL: v_insert_v64i32_37:

‎llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
1-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-WGP %s
2-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-WGP %s
3-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-WGP %s
4-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-CU %s
5-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED %s
6-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-CU %s
7-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-CU %s
8-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED %s
1+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-WGP %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-WGP %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-WGP %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-CU %s
5+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED %s
6+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-CU %s
7+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-CU %s
8+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED %s
99

1010
; GCN-LABEL: test_local_misaligned_v2:
1111
; GCN-DAG: ds_{{read2|load_2addr}}_b32

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
11
; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor -o %t.v4.ll
22
; RUN: sed 's/CODE_OBJECT_VERSION/600/g' %s | opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor -o %t.v6.ll
3-
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa < %t.v4.ll | FileCheck --check-prefixes=ALL,HSA,UNPACKED %s
4-
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa < %t.v4.ll | FileCheck --check-prefixes=ALL,HSA,UNPACKED %s
5-
; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=hawaii -mattr=+flat-for-global < %t.v4.ll | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s
6-
; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -mattr=+flat-for-global < %t.v4.ll | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s
7-
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+flat-for-global -mcpu=hawaii < %t.v4.ll | FileCheck -check-prefixes=ALL,MESA3D,UNPACKED %s
8-
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga < %t.v4.ll | FileCheck -check-prefixes=ALL,MESA3D,UNPACKED %s
9-
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a < %t.v4.ll | FileCheck -check-prefixes=ALL,PACKED-TID %s
10-
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %t.v4.ll | FileCheck -check-prefixes=ALL,PACKED-TID %s
11-
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx11-generic -amdgpu-enable-vopd=0 < %t.v6.ll | FileCheck -check-prefixes=ALL,PACKED-TID %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-unknown-amdhsa < %t.v4.ll | FileCheck --check-prefixes=ALL,HSA,UNPACKED %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-unknown-amdhsa < %t.v4.ll | FileCheck --check-prefixes=ALL,HSA,UNPACKED %s
5+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-- -mcpu=hawaii -mattr=+flat-for-global < %t.v4.ll | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s
6+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-- -mcpu=tonga -mattr=+flat-for-global < %t.v4.ll | FileCheck --check-prefixes=ALL,MESA,UNPACKED %s
7+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-unknown-mesa3d -mattr=+flat-for-global -mcpu=hawaii < %t.v4.ll | FileCheck -check-prefixes=ALL,MESA3D,UNPACKED %s
8+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga < %t.v4.ll | FileCheck -check-prefixes=ALL,MESA3D,UNPACKED %s
9+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx90a < %t.v4.ll | FileCheck -check-prefixes=ALL,PACKED-TID %s
10+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 < %t.v4.ll | FileCheck -check-prefixes=ALL,PACKED-TID %s
11+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=6 -mcpu=gfx11-generic -amdgpu-enable-vopd=0 < %t.v6.ll | FileCheck -check-prefixes=ALL,PACKED-TID %s
1212

1313
declare i32 @llvm.amdgcn.workitem.id.x() #0
1414
declare i32 @llvm.amdgcn.workitem.id.y() #0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir‎

Lines changed: 170 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,170 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s
3+
4+
---
5+
name: assert_sext_vgpr
6+
alignment: 4
7+
legalized: true
8+
tracksRegLiveness: true
9+
body: |
10+
bb.0:
11+
liveins: $vgpr0
12+
13+
; CHECK-LABEL: name: assert_sext_vgpr
14+
; CHECK: liveins: $vgpr0
15+
; CHECK-NEXT: {{ $}}
16+
; CHECK-NEXT: %copy:vgpr(s32) = COPY $vgpr0
17+
; CHECK-NEXT: %assert_sext:vgpr(s32) = G_ASSERT_SEXT %copy, 4
18+
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_sext(s32)
19+
%copy:_(s32) = COPY $vgpr0
20+
%assert_sext:_(s32) = G_ASSERT_SEXT %copy, 4
21+
S_ENDPGM 0, implicit %assert_sext
22+
...
23+
24+
---
25+
name: assert_sext_sgpr
26+
alignment: 4
27+
legalized: true
28+
tracksRegLiveness: true
29+
body: |
30+
bb.0:
31+
liveins: $sgpr8
32+
33+
; CHECK-LABEL: name: assert_sext_sgpr
34+
; CHECK: liveins: $sgpr8
35+
; CHECK-NEXT: {{ $}}
36+
; CHECK-NEXT: %copy:sgpr(s32) = COPY $sgpr8
37+
; CHECK-NEXT: %assert_sext:sgpr(s32) = G_ASSERT_SEXT %copy, 4
38+
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_sext(s32)
39+
%copy:_(s32) = COPY $sgpr8
40+
%assert_sext:_(s32) = G_ASSERT_SEXT %copy, 4
41+
S_ENDPGM 0, implicit %assert_sext
42+
...
43+
44+
---
45+
name: assert_sext_agpr
46+
alignment: 4
47+
legalized: true
48+
tracksRegLiveness: true
49+
body: |
50+
bb.0:
51+
liveins: $agpr0
52+
53+
; CHECK-LABEL: name: assert_sext_agpr
54+
; CHECK: liveins: $agpr0
55+
; CHECK-NEXT: {{ $}}
56+
; CHECK-NEXT: %copy:vgpr(s32) = COPY $agpr0
57+
; CHECK-NEXT: %assert_sext:vgpr(s32) = G_ASSERT_SEXT %copy, 4
58+
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_sext(s32)
59+
%copy:_(s32) = COPY $agpr0
60+
%assert_sext:_(s32) = G_ASSERT_SEXT %copy, 4
61+
S_ENDPGM 0, implicit %assert_sext
62+
...
63+
64+
---
65+
name: assert_sext_vgpr_regclass
66+
alignment: 4
67+
legalized: true
68+
tracksRegLiveness: true
69+
body: |
70+
bb.0:
71+
liveins: $vgpr0
72+
73+
; CHECK-LABEL: name: assert_sext_vgpr_regclass
74+
; CHECK: liveins: $vgpr0
75+
; CHECK-NEXT: {{ $}}
76+
; CHECK-NEXT: %copy:vgpr_32(s32) = COPY $vgpr0
77+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY %copy(s32)
78+
; CHECK-NEXT: %assert_sext:vgpr(s32) = G_ASSERT_SEXT [[COPY]], 4
79+
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_sext(s32)
80+
%copy:vgpr_32(s32) = COPY $vgpr0
81+
%assert_sext:_(s32) = G_ASSERT_SEXT %copy, 4
82+
S_ENDPGM 0, implicit %assert_sext
83+
...
84+
85+
---
86+
name: assert_sext_sgpr_regcllass
87+
alignment: 4
88+
legalized: true
89+
tracksRegLiveness: true
90+
body: |
91+
bb.0:
92+
liveins: $sgpr8
93+
94+
; CHECK-LABEL: name: assert_sext_sgpr_regcllass
95+
; CHECK: liveins: $sgpr8
96+
; CHECK-NEXT: {{ $}}
97+
; CHECK-NEXT: %copy:sgpr_32(s32) = COPY $sgpr8
98+
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY %copy(s32)
99+
; CHECK-NEXT: %assert_sext:sgpr(s32) = G_ASSERT_SEXT [[COPY]], 4
100+
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_sext(s32)
101+
%copy:sgpr_32(s32) = COPY $sgpr8
102+
%assert_sext:_(s32) = G_ASSERT_SEXT %copy, 4
103+
S_ENDPGM 0, implicit %assert_sext
104+
...
105+
106+
---
107+
name: assert_sext_vgpr_64
108+
alignment: 4
109+
legalized: true
110+
tracksRegLiveness: true
111+
body: |
112+
bb.0:
113+
liveins: $vgpr0_vgpr1
114+
115+
; CHECK-LABEL: name: assert_sext_vgpr_64
116+
; CHECK: liveins: $vgpr0_vgpr1
117+
; CHECK-NEXT: {{ $}}
118+
; CHECK-NEXT: %copy:vreg_64(s64) = COPY $vgpr0_vgpr1
119+
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY %copy(s64)
120+
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:vgpr(s64) = G_ASSERT_SEXT [[COPY]], 4
121+
; CHECK-NEXT: %assert_sext:vreg_64(s64) = COPY [[ASSERT_SEXT]](s64)
122+
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_sext(s64)
123+
%copy:vreg_64(s64) = COPY $vgpr0_vgpr1
124+
%assert_sext:vreg_64(s64) = G_ASSERT_SEXT %copy, 4
125+
S_ENDPGM 0, implicit %assert_sext
126+
...
127+
128+
---
129+
name: assert_sext_sgpr_64
130+
alignment: 4
131+
legalized: true
132+
tracksRegLiveness: true
133+
body: |
134+
bb.0:
135+
liveins: $sgpr0_sgpr1
136+
137+
; CHECK-LABEL: name: assert_sext_sgpr_64
138+
; CHECK: liveins: $sgpr0_sgpr1
139+
; CHECK-NEXT: {{ $}}
140+
; CHECK-NEXT: %copy:sreg_64(s64) = COPY $sgpr0_sgpr1
141+
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY %copy(s64)
142+
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:sgpr(s64) = G_ASSERT_SEXT [[COPY]], 4
143+
; CHECK-NEXT: %assert_sext:sreg_64(s64) = COPY [[ASSERT_SEXT]](s64)
144+
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_sext(s64)
145+
%copy:sreg_64(s64) = COPY $sgpr0_sgpr1
146+
%assert_sext:sreg_64(s64) = G_ASSERT_SEXT %copy, 4
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S_ENDPGM 0, implicit %assert_sext
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...
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---
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name: assert_sext_agpr_64
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alignment: 4
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $agpr0_agpr1
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; CHECK-LABEL: name: assert_sext_agpr_64
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; CHECK: liveins: $agpr0_agpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:areg_64(s64) = COPY $agpr0_agpr1
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY %copy(s64)
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; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:vgpr(s64) = G_ASSERT_SEXT [[COPY]], 4
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; CHECK-NEXT: %assert_sext:areg_64(s64) = COPY [[ASSERT_SEXT]](s64)
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; CHECK-NEXT: S_ENDPGM 0, implicit %assert_sext(s64)
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%copy:areg_64(s64) = COPY $agpr0_agpr1
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%assert_sext:areg_64(s64) = G_ASSERT_SEXT %copy, 4
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S_ENDPGM 0, implicit %assert_sext
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...

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