Digital VLSI ECE NTUA

Lab exercises for the DVLSI (Digital Very Large Scale Integration) course 2025.

Course Overview

This repository contains six progressive lab exercises covering fundamental and advanced digital design concepts:

Exercise 1: Basic VHDL Components

• 3-to-8 Decoders (behavioral and dataflow)
• 3-bit Counter with enable/reset
• 3-bit Shift Register implementations

Exercise 2: Arithmetic Units

• Half and Full Adders
• 4-bit Binary Adder
• BCD (Binary Coded Decimal) arithmetic units

Exercise 3: Advanced Arithmetic & Systolic Design

• Pipelined Full Adder designs
• Systolic array multipliers
• 2-bit pipeline multiplier

Exercise 4: Digital Signal Processing

• 8-tap FIR (Finite Impulse Response) filter
• MAC (Multiply-Accumulate) units
• Memory management (ROM/RAM)

Exercise 5: FPGA Integration

• ZYBO Zynq-7000 implementation of FIR filter
• Custom AXI IP core development
• Hardware-software co-design

Exercise 6: Debayering Filter Design and Implementation

• GBRG Bayer pattern debayering filter
• Real-time image processing pipeline
• Advanced FIFO-based data streaming

Repository Structure

Each exercise (exc1/ through exc6/) contains:

• source_files/: VHDL implementations and simulations
• README.MD: Detailed exercise description
• Lab PDF: Assignment specifications
• Report PDF: Implementation documentation

Contributors:

• @AntonisAk
• @vaniosh