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Commit 4747241

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author
Mariusz Glebocki
authored
Merge pull request chipsalliance#514 from antmicro/mglb/FixTests
systemverilog-plugin: Remove temporary test files.
2 parents 2ec0e35 + 62c6550 commit 4747241

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10 files changed

+43
-55
lines changed

10 files changed

+43
-55
lines changed

‎systemverilog-plugin/tests/Makefile‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,3 +35,9 @@ defaults_verify = true
3535
defines_verify = true
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formal_verify = true
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translate_off_verify = true
38+
39+
.PHONY: systemverilog_tests_clean
40+
systemverilog_tests_clean:
41+
@rm -rf $(foreach test,$(TESTS),$(test)/tmp)
42+
43+
clean: systemverilog_tests_clean

‎systemverilog-plugin/tests/break_continue/break_continue.tcl‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,12 +2,10 @@ yosys -import
22
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
33
yosys -import ;# ingest plugin commands
44

5-
set TMP_DIR /tmp
6-
if { [info exists ::env(TMPDIR) ] } {
7-
set TMP_DIR $::env(TMPDIR)
8-
}
5+
set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
6+
file mkdir $TMP_DIR
97

108
# Testing simple round-trip
11-
read_systemverilog -o $TMP_DIR/break-continue-test $::env(DESIGN_TOP).v
9+
read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
1210
prep
1311
write_table [test_output_path $::env(DESIGN_TOP).out]

‎systemverilog-plugin/tests/counter/counter.tcl‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,9 @@ yosys -import
22
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
33
yosys -import ;# ingest plugin commands
44

5-
set TMP_DIR /tmp
6-
if { [info exists ::env(TMPDIR) ] } {
7-
set TMP_DIR $::env(TMPDIR)
8-
}
5+
set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
6+
file mkdir $TMP_DIR
97

108
# Testing simple round-trip
11-
read_systemverilog -o $TMP_DIR/counter-test $::env(DESIGN_TOP).v
9+
read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
1210
write_verilog

‎systemverilog-plugin/tests/debug-flag/debug-flag.tcl‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,15 +2,13 @@ yosys -import
22
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
33
yosys -import ;# ingest plugin commands
44

5-
set TMP_DIR /tmp
6-
if { [info exists ::env(TMPDIR) ] } {
7-
set TMP_DIR $::env(TMPDIR)
8-
}
5+
set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
6+
file mkdir $TMP_DIR
97

108
# Testing simple round-trip
11-
read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-pkg.sv
12-
read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP)-buf.sv
13-
read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -defer $::env(DESIGN_TOP).v
14-
read_systemverilog -debug -odir $TMP_DIR/debug-flag-test -link
9+
read_systemverilog -debug -odir $TMP_DIR -defer $::env(DESIGN_TOP)-pkg.sv
10+
read_systemverilog -debug -odir $TMP_DIR -defer $::env(DESIGN_TOP)-buf.sv
11+
read_systemverilog -debug -odir $TMP_DIR -defer $::env(DESIGN_TOP).v
12+
read_systemverilog -debug -odir $TMP_DIR -link
1513
hierarchy
1614
write_verilog

‎systemverilog-plugin/tests/defaults/defaults.tcl‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,22 +2,20 @@ yosys -import
22
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
33
yosys -import ;# ingest plugin commands
44

5-
set TMP_DIR /tmp
6-
if { [info exists ::env(TMPDIR) ] } {
7-
set TMP_DIR $::env(TMPDIR)
8-
}
5+
set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
6+
file mkdir $TMP_DIR
97

108
# Define forbidden value
119
systemverilog_defaults -add -DPAKALA
1210
# Stash it
1311
systemverilog_defaults -push
1412
systemverilog_defaults -clear
15-
read_systemverilog -o $TMP_DIR/defaults-test $::env(DESIGN_TOP).v
13+
read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
1614
# Allow parsing the module again
1715
delete top
1816
systemverilog_defaults -pop
1917
# Skip check for forbidden value
2018
systemverilog_defaults -add -Pbypass=1
21-
read_systemverilog -o $TMP_DIR/defaults-test $::env(DESIGN_TOP).v
19+
read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
2220
hierarchy
2321
write_verilog

‎systemverilog-plugin/tests/defines/defines.tcl‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,14 +2,12 @@ yosys -import
22
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
33
yosys -import ;# ingest plugin commands
44

5-
set TMP_DIR /tmp
6-
if { [info exists ::env(TMPDIR) ] } {
7-
set TMP_DIR $::env(TMPDIR)
8-
}
5+
set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
6+
file mkdir $TMP_DIR
97

108
systemverilog_defines -DPONA
119
systemverilog_defines -DPAKALA
1210
systemverilog_defines -UPAKALA
13-
read_systemverilog -o $TMP_DIR/defines-test $::env(DESIGN_TOP).v
11+
read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v
1412
hierarchy
1513
write_verilog

‎systemverilog-plugin/tests/formal/formal.tcl‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,9 @@ yosys -import
22
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
33
yosys -import ;# ingest plugin commands
44

5-
set TMP_DIR /tmp
6-
if { [info exists ::env(TMPDIR) ] } {
7-
set TMP_DIR $::env(TMPDIR)
8-
}
5+
set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
6+
file mkdir $TMP_DIR
97

10-
read_systemverilog -o $TMP_DIR/formal-test -formal $::env(DESIGN_TOP).v
8+
read_systemverilog -o $TMP_DIR -formal $::env(DESIGN_TOP).v
119
hierarchy
1210
write_verilog

‎systemverilog-plugin/tests/report-flag/report-flag.tcl‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,15 +2,13 @@ yosys -import
22
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
33
yosys -import ;# ingest plugin commands
44

5-
set TMP_DIR /tmp
6-
if { [info exists ::env(TMPDIR) ] } {
7-
set TMP_DIR $::env(TMPDIR)
8-
}
5+
set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
6+
file mkdir $TMP_DIR
97

108
# Testing simple round-trip
11-
read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-pkg.sv
12-
read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP)-buf.sv
13-
read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -defer $::env(DESIGN_TOP).v
14-
read_systemverilog -report $TMP_DIR/report-flag-test -odir $TMP_DIR/report-flag-test -link
9+
read_systemverilog -report $TMP_DIR -odir $TMP_DIR -defer $::env(DESIGN_TOP)-pkg.sv
10+
read_systemverilog -report $TMP_DIR -odir $TMP_DIR -defer $::env(DESIGN_TOP)-buf.sv
11+
read_systemverilog -report $TMP_DIR -odir $TMP_DIR -defer $::env(DESIGN_TOP).v
12+
read_systemverilog -report $TMP_DIR -odir $TMP_DIR -link
1513
hierarchy
1614
write_verilog

‎systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,15 +2,13 @@ yosys -import
22
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
33
yosys -import ;# ingest plugin commands
44

5-
set TMP_DIR /tmp
6-
if { [info exists ::env(TMPDIR) ] } {
7-
set TMP_DIR $::env(TMPDIR)
8-
}
5+
set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
6+
file mkdir $TMP_DIR
97

108
# Testing simple round-trip
11-
read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-pkg.sv
12-
read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP)-buf.sv
13-
read_systemverilog -odir $TMP_DIR/separate-compilation-test -defer $::env(DESIGN_TOP).v
14-
read_systemverilog -odir $TMP_DIR/separate-compilation-test -link
9+
read_systemverilog -odir $TMP_DIR -defer $::env(DESIGN_TOP)-pkg.sv
10+
read_systemverilog -odir $TMP_DIR -defer $::env(DESIGN_TOP)-buf.sv
11+
read_systemverilog -odir $TMP_DIR -defer $::env(DESIGN_TOP).v
12+
read_systemverilog -odir $TMP_DIR -link
1513
hierarchy
1614
write_verilog

‎systemverilog-plugin/tests/translate_off/translate_off.tcl‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,7 @@ yosys -import
22
if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
33
yosys -import ;# ingest plugin commands
44

5-
set TMP_DIR /tmp
6-
if { [info exists ::env(TMPDIR) ] } {
7-
set TMP_DIR $::env(TMPDIR)
8-
}
5+
set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
6+
file mkdir $TMP_DIR
97

10-
read_systemverilog -o $TMP_DIR/translate_off-test $::env(DESIGN_TOP).v
8+
read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v

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