Merge pull request chipsalliance#515 from hzeller/20230516-expand-env-var

Tcl-tests: expand environment variables.

Author: hzeller

systemverilog-plugin/tests/break_continue/break_continue.tcl

@@ -2,7 +2,7 @@ yosys -import
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/counter/counter.tcl

@@ -2,7 +2,7 @@ yosys -import
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/debug-flag/debug-flag.tcl

@@ -2,7 +2,7 @@ yosys -import
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/defaults/defaults.tcl

@@ -2,7 +2,7 @@ yosys -import
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Define forbidden value

systemverilog-plugin/tests/defines/defines.tcl

@@ -2,7 +2,7 @@ yosys -import
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 systemverilog_defines -DPONA

systemverilog-plugin/tests/formal/formal.tcl

@@ -2,7 +2,7 @@ yosys -import
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 read_systemverilog -o $TMP_DIR -formal $::env(DESIGN_TOP).v

systemverilog-plugin/tests/report-flag/report-flag.tcl

@@ -2,7 +2,7 @@ yosys -import
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl

@@ -2,7 +2,7 @@ yosys -import
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/translate_off/translate_off.tcl

@@ -2,7 +2,7 @@ yosys -import
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v