Mention use of CPTR_EL3.ESM bit to untrap SME instns

Author: stephentheobald-arm

content/learning-paths/cross-platform/sme/_index.md

@@ -23,7 +23,6 @@ armips:
 
 tools_software_languages:
     - Coding
-    - Trusted Firmware
     - Arm Development Studio
 
 operatingsystems:

content/learning-paths/cross-platform/sme/matrix-multiply-example.md

@@ -58,9 +58,9 @@ Execution can be controlled by the `Debug Control` pane icon bar (eg `Step Instr
 3. In the Registers view, expand AArch64 > System > PSTATE > SVCR. Notice the ZA bit is currently 0, meaning the ZA array storage is invalid and not accessible. This will change to 1 later, when an SMSTART instruction is executed.
 4. In `main.c`, observe that `main()` initialises the sizes (M, N, K) of the matrices, prints a welcome banner, then disables SVE and SIMD traps.
 5. Set a breakpoint on the `disable_sve_traps` function with `break disable_sve_traps` and run to it (press F8). It is written in assembler.
-6. In the Registers view, expand AArch64 > System > Secure > CPTR_EL3. The EZ and TFP bits reset to an architecturally unknown value on startup. To avoid SVE and SIMD instructions being trapped, the EZ bit must be set to 1 and the TFP bit must be cleared to 0, respectively.
+6. In the Registers view, expand AArch64 > System > Secure > CPTR_EL3. To avoid SME, SVE, or SIMD instructions being trapped, the ESM and EZ bits must be set to 1 and the TFP bit must be cleared to 0, respectively, in CPTR_EL3. These bits reset to an architecturally unknown value on startup.
 7. In the Debug Control view, select Stepping By Instruction (press F10) to switch stepping mode to instruction level.
-8. Single-step (press F5) over the MRS, BIC, ORR, MSR, ISB instructions, and observe the EZ bit being set to 1 and the TFP bit being cleared, thereby disabling the SVE and SIMD traps.
+8. Single-step (press F5) over the MRS, BIC, ORR, MSR, ISB instructions, and observe those bits are set/cleared as required.
 9. The vector length is read at run-time using an `RDSVL` instruction.  To see this, set a breakpoint on `sve_cntw()` with `break sve_cntw` and run to it (press F8).  Single-step (press F5) the `RDSVL` instruction.  The value returned by `RDSVL` in the specified register is SVL DIV 8.
 10. In the Debug Control view, select Stepping By Source (press F10) to switch stepping mode back to C source level.
 11. The C code then initializes the matLeft and matRight arrays with random single-precision floating-point values. The input (and result) matrices are stored in memory in a row-major memory layout. To see the input values matLeft and matRight, set a breakpoint on the call to matmul() on line 85 and run to it (press F8). Open the Memory view, select Xn (Format) > Float > 4 bytes, then enter either matLeft or matRight in the address field (top-left text entry box).