Updated from Andy Pickard’s feedback (second batch)

Author: stephentheobald-arm

content/learning-paths/cross-platform/sme/ZA.png

@@ -2,14 +2,14 @@
 review:
     - questions:
         question: >
-            What are the supported sizes for the ZA storage in SME?
+            How large is the ZA storage?
         answers:
-            - 16x16, 32x32, 64x64, 128x128, and 256x256 bits
-            - 16x16, 32x32, 64x64, 128x128, and 256x256 bytes
-            - 16x16, 32x32, 64x64, 128x128, and 256x256 floats
+            - (SVL/8) x (SVL/8) bits
+            - (SVL/8) x (SVL/8) bytes
+            - (SVL/8) x (SVL/8) floats
         correct_answer: 2
         explanation: >
-            The ZA storage is two-dimensional array of 8-bit elements, a power of two in the range 16 to 256 bytes.
+            The ZA storage is a two-dimensional array of (SVL/8) x (SVL/8) bytes. Since SVL is a power of two in the range 128 to 2048 bits, (SVL/8) will be a power of two in the range 16 to 256 bytes.
 
     - questions:
         question: >

content/learning-paths/cross-platform/sme/_review.md

@@ -6,7 +6,7 @@ weight: 2
 layout: learningpathall
 ---
 
-The [Scalable Matrix Extension](https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture) (SME) is a system solution consisting of hardware and software components to efficiently process matrices, including matrix tile storage and outer-product operations.
+The [Scalable Matrix Extension](https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/scalable-matrix-extension-armv9-a-architecture) (SME) is a system solution consisting of hardware components to efficiently process matrices.
 
 SME introduces:
 * A register array storage ("ZA") capable of holding two-dimensional matrix tiles.
@@ -15,14 +15,19 @@ SME introduces:
 * Instructions that transfer a vector to or from a tile row or column.
 * System registers and fields that identify the presence and capabilities of SME, and enable and control its behavior at each Exception level.
 
-The ZA storage is a two-dimensional array of SVL{{< sub "B" >}} x SVL{{< sub "B" >}} bytes, where SVL{{< sub "B" >}} is the number of 8-bit elements, a power of two in the range 16 to 256 bytes.
-The ZA array can be accessed as vectors of SVL bits, with element sizes 8-bit, 16-bit, 32-bit, 64-bit, or 128-bit.
+The ZA storage is a two-dimensional array of width SVL bits, and height equal to its width in bytes, in other words, (SVL / 8) rows. 
+SVL (the Effective Streaming SVE Vector Length) can be configured in software, and is a power of two in the range 128 to 2048 bits inclusive.
 
-The ZA array can also be accessed as tiles.  A ZA tile is a square, two-dimensional sub-array of elements within the ZA array, and can be accessed as vectors of 8-bit, 16-bit, 32-bit, 64-bit, or 128-bit elements.
-A ZA tile slice is a one-dimensional set of horizontally or vertically contiguous elements within a ZA tile.
+The ZA storage is accessed as tiles. A ZA tile is a square, two-dimensional sub-array of elements within the ZA array, whose elements must all be the same width, which can be 8-bit, 16-bit, 32-bit, 64-bit, or 128-bit.
 
-![example image alt-text#center](ZA.png "Figure 1. The ZA storage, shown for SVL{{< sub "B" >}} = 32, organized as 32-bit floats, and the mapping to horizontal and vertical slices of ZA0-3 tiles.
-In this arrangement, there are SVL{{< sub "B" >}} = 32 rows, and SVL{{< sub "S" >}} = 8 columns of 32-bit elements.")
+The tile width is the same as the ZA storage width, which is always SVL bits. If N = SVL/8 then the ZA storage would be N rows x N bytes in size. 
+When accessing the tile as 16-bit halfwords, it would only be N/2 halfwords wide. Since tiles are square, it would also be N/2 rows high, and therefore there is space in the ZA storage for two such tiles.
+
+Similarly, when accessing 32-bit elements, tiles would have height and width both equal to N/4, so there would be four such tiles in the ZA storage. This trend continues so that there would be 16 tiles of element width 128-bits.
+
+You can read or write a ZA tile slice, which is a one-dimensional vector representing a complete row or column within a tile slice.
+
+![example image alt-text#center](ZA.png "Figure 1. The ZA storage, accessed by 32-bit elements, shown for SVL = 256 bits, and showing the mapping to horizontal and vertical slices of the four ZA0-3 tiles.")
 
 The Scalable Matrix Extension version 2 (SME2) extends the SME architecture to increase the number of applications that can benefit from the computational efficiency of SME, beyond its initial focus on outer products and matrix-matrix multiplication.  SME2 adds:
 * Data processing instructions with multi-vector operands and a multi-vector predication mechanism.