mspm0 int group support #61
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MSPM0 (G and L series so far) declare the NVIC interrupts 0 and 1 as shared interrupts, called interrupt group 0 and 1 respectively. Such group can handle up to 8 different "interrupt" and thus require to be differentiated at runtime. Signed-off-by: Tomasz Bursztyka <[email protected]>
Each gpio shares the same interrupt but has a unique interrupt index within the same interrupt (called interrupt group). Signed-off-by: Tomasz Bursztyka <[email protected]>
Instead of connecting to the same interrupt, register to the relevant interrupt group. Uniqueness of interrupt index enables the relevant ISR to be called direcly with the proper device. Signed-off-by: Tomasz Bursztyka <[email protected]>
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See section 3.3.1.2 in mspm0's datasheet