CIMFlow Simulator

A cycle-accurate, power-aware simulator for Compute-In-Memory (CIM) architectures.

Part of the CIMFlow framework — see the main CIMFlow repository for the complete compilation and simulation toolchain.

Overview

CIMFlow Simulator is the hardware simulation component of the CIMFlow framework, designed to model and evaluate Compute-In-Memory architectures. Built on SystemC, it provides detailed cycle-level simulation with integrated power modeling, enabling researchers and architects to explore CIM-based computing systems for applications including neural network inference and other compute-intensive workloads.

Key Features

• Cycle-Accurate Simulation: Precise timing modeling using SystemC for hardware-level accuracy
• Power Modeling: Integrated static and dynamic power analysis for all components
• Flexible Architecture: Configurable chip, core, memory hierarchy, and network parameters
• Memory Hierarchy: Configurable local memories (SRAM, register buffers) and global memory
• Profiling Tools: Built-in performance and energy profiling capabilities

Quick Start

Prerequisites

• C++17 compatible compiler
• CMake 3.20 or higher
• SystemC (included as submodule)

Building

# Clone the repository
git clone https://github.com/BUAA-CI-LAB/CIMFlow-Simulator.git
cd CIMFlow-Simulator

# Initialize submodules
git submodule update --init --recursive

# Run the installation script
./install.sh

Alternatively, you can build manually:

mkdir build && cd build
cmake ..
cmake --build . -j$(nproc)

The main simulator executable will be available as cim-simulator in the build directory.

Basic Usage

# Run simulation with configuration files
./cim-simulator \
    <chip_config.json> \
    <instruction_file.json> \
    -o <report_path> \
    --format <output_format>

Configuration

The simulator is configured via JSON files. See config/config_template.json for a complete example with:

• Chip and core count configuration
• Control unit, register unit, and execution unit parameters
• CIM macro organization and power specifications
• Memory hierarchy setup
• Simulation parameters (clock period, simulation mode)

Project Structure

.
├── src/                    # Source code
│   ├── chip/              # Chip-level components
│   ├── core/              # Core architecture
│   ├── memory/            # Memory system
│   ├── network/           # Network infrastructure
│   ├── isa/               # Instruction set architecture
│   ├── simulator/         # Simulator main classes
│   └── util/              # Utilities and helpers
├── config/                # Configuration files
├── thirdparty/            # Third-party dependencies
└── CMakeLists.txt         # Build configuration

Dependencies

The simulator uses the following third-party libraries (included as submodules):

• SystemC: Cycle-accurate hardware simulation framework
• fmt: Modern C++ string formatting
• nlohmann/json: JSON parsing and serialization
• argparse: Command-line argument parsing
• better-enums: Enhanced C++ enumerations

Maintainers

Current Maintainers:

• Yingjie Qi
• Xiao Ma

Previous Maintainer:

• Yikun Wang

License

This project is licensed under the Apache License 2.0 - see the LICENSE file for details.

Contributing

Contributions are welcome! Please feel free to submit issues and pull requests.