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‎ARM-Project/ARM-Project.cache/wt/project.wpc‎

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version:1
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6d6f64655f636f756e7465727c4755494d6f6465:20
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6d6f64655f636f756e7465727c4755494d6f6465:21
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eof:

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/compile.bat‎

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@@ -6,7 +6,7 @@ REM Filename : compile.bat
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REM Simulator : Xilinx Vivado Simulator
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REM Description : Script for compiling the simulation design source files
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REM
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REM Generated by Vivado on Tue Feb 27 16:52:50 -0600 2024
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REM Generated by Vivado on Wed Feb 28 11:32:00 -0600 2024
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REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
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REM
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REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/elaborate.bat‎

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@@ -6,7 +6,7 @@ REM Filename : elaborate.bat
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REM Simulator : Xilinx Vivado Simulator
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REM Description : Script for elaborating the compiled design
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REM
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REM Generated by Vivado on Tue Feb 27 16:52:51 -0600 2024
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REM Generated by Vivado on Wed Feb 28 11:32:01 -0600 2024
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REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
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REM
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REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/elaborate.log‎

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Vivado Simulator v2021.2
22
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
3-
Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot iDecode_test_behav xil_defaultlib.iDecode_test xil_defaultlib.glbl -log elaborate.log
3+
Running: C:/XilinxVitis/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot iDecode_test_behav xil_defaultlib.iDecode_test xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
7-
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:136]
8-
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:165]
9-
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:192]
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WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:219]
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WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:246]
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WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:273]
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WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:300]
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WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:327]
15-
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:354]
16-
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:381]
7+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:136]
8+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:165]
9+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:192]
10+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:219]
11+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:246]
12+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:273]
13+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:300]
14+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:327]
15+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:354]
16+
WARNING: [VRFC 10-3597] non-void function 'verify_control_signals' called as a task without void casting [C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv:381]
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling package xil_defaultlib.verification
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Compiling module xil_defaultlib.instr_parse
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Compiling module xil_defaultlib.control
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Compiling module xil_defaultlib.regfile
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Compiling module xil_defaultlib.sign_extender
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Compiling module xil_defaultlib.mux(SIZE=5)
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Compiling module xil_defaultlib.iDecode
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Compiling module xil_defaultlib.oscillator
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Compiling module xil_defaultlib.delay
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Compiling module xil_defaultlib.delay(DELAYAMT=7)
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Compiling module xil_defaultlib.iDecode_test
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot iDecode_test_behav
18+
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/iDecode_test_behav.wdb‎

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‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/simulate.bat‎

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REM Simulator : Xilinx Vivado Simulator
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REM Description : Script for simulating the design by launching the simulator
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REM
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REM Generated by Vivado on Tue Feb 27 15:50:05 -0600 2024
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REM Generated by Vivado on Wed Feb 28 11:31:49 -0600 2024
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REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
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REM
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REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
@@ -15,8 +15,8 @@ REM usage: simulate.bat
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REM
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REM ****************************************************************************
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REM simulate design
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echo "xsim iDecode_test_behav -key {Behavioral:sim_1:Functional:iDecode_test} -tclbatch iDecode_test.tcl -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/register_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/adder_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/mux_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/instr_mem_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/iFetch_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/instr_parse_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/regfile_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/control_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/sign_extender_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/iDecode_test_behav.wcfg -log simulate.log"
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call xsim iDecode_test_behav -key {Behavioral:sim_1:Functional:iDecode_test} -tclbatch iDecode_test.tcl -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/register_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/adder_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/mux_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/instr_mem_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/iFetch_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/instr_parse_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/regfile_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/control_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/sign_extender_test_behav.wcfg -view C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Project/iDecode_test_behav.wcfg -log simulate.log
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echo "xsim iDecode_test_behav -key {Behavioral:sim_1:Functional:iDecode_test} -tclbatch iDecode_test.tcl -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/register_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/adder_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/mux_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_mem_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iFetch_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_parse_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/regfile_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/control_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/sign_extender_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iDecode_test_behav.wcfg -log simulate.log"
19+
call xsim iDecode_test_behav -key {Behavioral:sim_1:Functional:iDecode_test} -tclbatch iDecode_test.tcl -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/register_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/adder_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/mux_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_mem_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iFetch_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/instr_parse_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/regfile_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/control_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/sign_extender_test_behav.wcfg -view C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Project/iDecode_test_behav.wcfg -log simulate.log
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if "%errorlevel%"=="0" goto SUCCESS
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if "%errorlevel%"=="1" goto END
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:END

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/simulate.log‎

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******* END TEST RESULTS *******
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$finish called at time : 105 ns : File "C:/Users/reese/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv" Line 389
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$finish called at time : 105 ns : File "C:/Users/reese_ford1/Documents/GitHub/ARM-Lab/ARM-Lab/code/2_decode/iDecode_test.sv" Line 389

‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/xelab.pb‎

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‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/xsim.dir/iDecode_test_behav/obj/xsim_0.win64.obj‎

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‎ARM-Project/ARM-Project.sim/sim_1/behav/xsim/xsim.dir/iDecode_test_behav/obj/xsim_1.c‎

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void simulate(char *dp)
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{
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iki_register_root_pointers(14, 10344, -5,0,14808, -5,0,15544, -5,0,16832, -5,0,14992, -5,0,15176, -5,0,16096, -5,0,15728, -5,0,16280, -5,0,14624, -5,0,15360, -5,0,16464, -5,0,15912, -5,0,16648, -5,0) ;
123+
iki_register_root_pointers(14, 16648, -5,0,16280, -5,0,16832, -5,0,15912, -5,0,16096, -5,0,16464, -5,0,14624, -5,0,15544, -5,0,14808, -5,0,14992, -5,0,15176, -5,0,15360, -5,0,15728, -5,0,10344, -5,0) ;
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iki_schedule_processes_at_time_zero(dp, "xsim.dir/iDecode_test_behav/xsim.reloc");
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// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
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iki_execute_processes();

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