IoT + More Test Panel (#408)

A panel of mostly misc IoT devices, meant to be a fabrication test of
the recent compiler and infrastructural changes. And the sublayout KiCad
plugin.

Top-level boards:
- add BLE joystick
- replace can-adapter with OBD adapter
- add IoT rollerblinds and curtain crawler, all variations on a IoT
brushed-DC motor driver
- replace IoT LED driver with a puck design and higher frequency LED
drivers

Library additions:
- Change JLC postprocessing script to support merging BoMs, for
panelization
- Add SeriesPowerFuse to support non-PPTC fuses
- Add base categories MagneticSensor and MagneticSwitch, distinct from
Magnetometer which has a analog response
  - Add A1304 linear hall-effect sensor
  - Add AH1806 hall effect switch
- Add I2C bitbang adpater, to convert digital lines to I2C lines
- Add Nano2 fuseholder
- Add XBox Elite joystick block and footprint
- Add TPS92200 buck LED driver, higher frequency (and smaller inductor)
than the current one
- Add DRV8870 DC motor driver
- Add JST XH, Molex Picoblade connectors.
- Add JST PH connector super-class.
- Add J1962 (OBDII) footprint
- Add Mp2722 bidirectional buck converter for single-cell LiIon

Fixes:
- Add optional signal_out_abs to AnalogSource.from_supply
- MCP73831: make stat output line optional
- Add CAN (TWAI) to ESP32C3

Author: ducky64

edg/BoardTop.py

@@ -34,6 +34,7 @@ def refinements(self) -> Refinements:
         (Fpc050Bottom, HiroseFh12sh),
         (UsbEsdDiode, Tpd2e009),
         (CanEsdDiode, Pesd1can),
+        (Fuse, Nano2Fuseholder),
         (TestPoint, TeRc),
 
         (SwdCortexTargetConnector, SwdCortexTargetHeader),
@@ -77,6 +78,7 @@ def refinements(self) -> Refinements:
         (Resistor, JlcResistor),
         (Capacitor, JlcCapacitor),
         (Inductor, JlcInductor),
+        (AluminumCapacitor, JlcAluminumCapacitor),
         (FerriteBead, JlcFerriteBead),
         (PptcFuse, JlcPptcFuse),
         (ResistorArray, JlcResistorArray),

edg/abstract_parts/AbstractFuse.py

@@ -68,6 +68,41 @@ def contents(self):
                  "operating voltage not within rating")
 
 
+class SeriesPowerFuse(Protection):
+  """Series fuse for power applications"""
+  FUSE_TYPE = Fuse
+
+  @init_in_parent
+  def __init__(self, trip_current: RangeLike) -> None:
+    super().__init__()
+
+    self.pwr_out = self.Port(VoltageSource.empty(), [Output])  # forward declaration
+    self.pwr_in = self.Port(VoltageSink.empty(), [Power, Input])  # forward declaration
+
+    self.fuse = self.Block(self.FUSE_TYPE(
+      trip_current=trip_current,
+      hold_current=(self.pwr_out.link().current_drawn.upper(), float('inf')),
+      voltage=self.pwr_in.link().voltage
+    ))
+    self.connect(self.pwr_in, self.fuse.a.adapt_to(VoltageSink(
+      voltage_limits=self.fuse.actual_voltage_rating,  # TODO: eventually needs a ground ref
+      current_draw=self.pwr_out.link().current_drawn
+    )))
+    self.connect(self.pwr_out, self.fuse.b.adapt_to(VoltageSource(
+      voltage_out=self.pwr_in.link().voltage,  # ignore voltage drop
+      current_limits=(0, self.fuse.actual_hold_current.lower())
+    )))
+
+  def connected(self, pwr_in: Optional[Port[VoltageLink]] = None, pwr_out: Optional[Port[VoltageLink]] = None) -> \
+          'SeriesPowerFuse':
+    """Convenience function to connect both ports, returning this object so it can still be given a name."""
+    if pwr_in is not None:
+      cast(Block, builder.get_enclosing_block()).connect(pwr_in, self.pwr_in)
+    if pwr_out is not None:
+      cast(Block, builder.get_enclosing_block()).connect(pwr_out, self.pwr_out)
+    return self
+
+
 @abstract_block
 class PptcFuse(Fuse):
   """PPTC self-resetting fuse"""
@@ -97,34 +132,5 @@ def _row_generate(self, row: PartsTableRow) -> None:
     self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING])
 
 
-class SeriesPowerPptcFuse(Protection):
-  """Series fuse for power applications"""
-  @init_in_parent
-  def __init__(self, trip_current: RangeLike) -> None:
-    super().__init__()
-
-    self.pwr_out = self.Port(VoltageSource.empty(), [Output])  # forward declaration
-    self.pwr_in = self.Port(VoltageSink.empty(), [Power, Input])  # forward declaration
-
-    self.fuse = self.Block(PptcFuse(
-      trip_current=trip_current,
-      hold_current=(self.pwr_out.link().current_drawn.upper(), float('inf')),
-      voltage=self.pwr_in.link().voltage
-    ))
-    self.connect(self.pwr_in, self.fuse.a.adapt_to(VoltageSink(
-      voltage_limits=self.fuse.actual_voltage_rating,  # TODO: eventually needs a ground ref
-      current_draw=self.pwr_out.link().current_drawn
-    )))
-    self.connect(self.pwr_out, self.fuse.b.adapt_to(VoltageSource(
-      voltage_out=self.pwr_in.link().voltage,  # ignore voltage drop
-      current_limits=(0, self.fuse.actual_hold_current.lower())
-    )))
-
-  def connected(self, pwr_in: Optional[Port[VoltageLink]] = None, pwr_out: Optional[Port[VoltageLink]] = None) -> \
-      'SeriesPowerPptcFuse':
-    """Convenience function to connect both ports, returning this object so it can still be given a name."""
-    if pwr_in is not None:
-      cast(Block, builder.get_enclosing_block()).connect(pwr_in, self.pwr_in)
-    if pwr_out is not None:
-      cast(Block, builder.get_enclosing_block()).connect(pwr_out, self.pwr_out)
-    return self
+class SeriesPowerPptcFuse(SeriesPowerFuse):
+  FUSE_TYPE = PptcFuse

edg/abstract_parts/AbstractInductor.py

@@ -1,4 +1,4 @@
-from typing import Dict, Optional, cast
+from typing import Dict, Optional, cast, Any
 
 from ..electronics_model import *
 from .PartsTable import PartsTableColumn, PartsTableRow, ExperimentalUserFnPartsTable
@@ -143,7 +143,6 @@ def __init__(self, *args, **kwargs) -> None:
                          self.experimental_filter_fn)
 
   def _row_filter(self, row: PartsTableRow) -> bool:
-    # TODO eliminate arbitrary DCR limit in favor of exposing max DCR to upper levels
     filter_fn_str = self.get(self.experimental_filter_fn)
     if filter_fn_str:
       filter_fn = ExperimentalUserFnPartsTable.deserialize_fn(filter_fn_str)
@@ -164,6 +163,10 @@ def _row_generate(self, row: PartsTableRow) -> None:
     self.assign(self.actual_frequency_rating, row[self.FREQUENCY_RATING])
     self.assign(self.actual_resistance_dc, row[self.DC_RESISTANCE])
 
+  @classmethod
+  def _row_sort_by(cls, row: PartsTableRow) -> Any:
+    return row[cls.DC_RESISTANCE].center()
+
 
 class SeriesPowerInductor(DiscreteApplication):
   """VoltageSource/Sink-typed series inductor for power filtering"""

edg/abstract_parts/Categories.py

@@ -238,7 +238,19 @@ class LightSensor(Sensor):
 
 
 @abstract_block
-class Magnetometer(Sensor):
+class MagneticSensor(Sensor):
+  pass
+
+
+@abstract_block
+class MagneticSwitch(MagneticSensor):
+  """A switch that is activated by a magnetic field, including omnipolar and bipolar devices."""
+  pass
+
+
+@abstract_block
+class Magnetometer(MagneticSensor):
+  """Linear response magnetic field sensor, potentially with multiple axes"""
   pass
 
 

edg/abstract_parts/I2cBitBang.py

@@ -0,0 +1,36 @@
+from typing import cast
+
+from ..electronics_model import *
+from .Categories import *
+
+
+class I2cControllerBitBang(BitBangAdapter, Block):
+  """Bit-bang adapter for I2C controller"""
+  @staticmethod
+  def digital_external_from_link(link_port: DigitalBidir) -> DigitalBidir:
+    """Creates a DigitalBidir model that is the external-facing port that exports from
+    an internal-facing (link-side) port. The internal-facing port should be ideal.
+    These are basically the semantics of a DigitalBidir bridge.
+    TODO: unify code w/ DigitalBidir bridge?"""
+    return DigitalBidir(
+      voltage_out=link_port.link().voltage, current_draw=link_port.link().current_drawn,
+      voltage_limits=link_port.link().voltage_limits, current_limits=link_port.link().current_limits,
+      output_thresholds=link_port.link().output_thresholds, input_thresholds=link_port.link().input_thresholds,
+      pulldown_capable=link_port.link().pulldown_capable, pullup_capable=link_port.link().pullup_capable
+    )
+
+  def __init__(self) -> None:
+    super().__init__()
+    self.i2c = self.Port(I2cController.empty(), [Output])
+    self.scl = self.Port(DigitalBidir.empty())
+    self.sda = self.Port(DigitalBidir.empty())
+
+  def contents(self) -> None:
+    super().contents()
+    self.connect(self.i2c.scl, self.scl)
+    self.connect(self.i2c.sda, self.sda)
+
+  def connected_from(self, scl: Port[DigitalLink], sda: Port[DigitalLink]) -> 'I2cControllerBitBang':
+    cast(Block, builder.get_enclosing_block()).connect(scl, self.scl)
+    cast(Block, builder.get_enclosing_block()).connect(sda, self.sda)
+    return self

edg/abstract_parts/__init__.py

@@ -15,8 +15,8 @@
 from .Categories import PowerConditioner, PowerSwitch, MotorDriver, BrushedMotorDriver, BldcDriver
 from .Categories import PowerSource, Connector, ProgrammingConnector
 from .Categories import HumanInterface, Display, Lcd, Oled, EInk, Light
-from .Categories import Sensor, CurrentSensor, Accelerometer, Gyroscope, Magnetometer, DistanceSensor, Microphone, \
-    Camera, LightSensor
+from .Categories import Sensor, CurrentSensor, Accelerometer, Gyroscope, MagneticSensor, MagneticSwitch, Magnetometer,\
+    DistanceSensor, Microphone, Camera, LightSensor
 from .Categories import EnvironmentalSensor, TemperatureSensor, HumiditySensor, PressureSensor, GasSensor
 from .Categories import Label, Testing, TypedJumper, TypedTestPoint, InternalSubcircuit, DeprecatedBlock, Mechanical
 from .Categories import MultipackDevice
@@ -74,7 +74,7 @@
 from .PowerCircuits import HalfBridge, FetHalfBridge, HalfBridgeIndependent, HalfBridgePwm, FetHalfBridgeIndependent,\
     FetHalfBridgePwmReset
 from .AbstractLedDriver import LedDriver, LedDriverPwm, LedDriverSwitchingConverter
-from .AbstractFuse import Fuse, PptcFuse, FuseStandardFootprint, TableFuse, SeriesPowerPptcFuse
+from .AbstractFuse import Fuse, SeriesPowerFuse, PptcFuse, FuseStandardFootprint, TableFuse, SeriesPowerPptcFuse
 from .AbstractCrystal import Crystal, TableCrystal, OscillatorReference, CeramicResonator
 from .AbstractOscillator import Oscillator, TableOscillator
 from .AbstractDebugHeaders import SwdCortexTargetConnector, SwdCortexTargetConnectorReset, \
@@ -92,6 +92,7 @@
 from .DigitalIsolator import DigitalIsolator
 from .I2cPullup import I2cPullup
 from .UsbBitBang import UsbBitBang
+from .I2cBitBang import I2cControllerBitBang
 
 from .IoController import BaseIoController, IoController, IoControllerPowerRequired, BaseIoControllerPinmapGenerator
 from .IoControllerExportable import BaseIoControllerExportable

edg/electronics_model/AnalogPort.py

@@ -175,14 +175,19 @@ class AnalogSource(AnalogBase):
   @staticmethod
   def from_supply(neg: Port[GroundLink], pos: Port[VoltageLink], *,
                   signal_out_bound: Optional[Tuple[FloatLike, FloatLike]] = None,
+                  signal_out_abs: Optional[RangeLike] = None,
                   current_limits: RangeLike = RangeExpr.ALL,
                   impedance: RangeLike = RangeExpr.ZERO):
     supply_range = VoltageLink._supply_voltage_range(neg, pos)
     if signal_out_bound is not None:
+      assert signal_out_abs is None
       # signal limit bounds specified as (lower bound added to limit, upper bound added to limit)
       # typically (positive, negative)
       signal_out: RangeLike = (supply_range.lower() + signal_out_bound[0],
                                supply_range.upper() + signal_out_bound[1])
+    elif signal_out_abs is not None:
+      assert signal_out_bound is None
+      signal_out = signal_out_abs
     else:  # generic default
       signal_out = supply_range
 

edg/electronics_model/DigitalPorts.py

@@ -310,6 +310,7 @@ def __init__(self, voltage_out: RangeLike = RangeExpr.ZERO,
 
   @staticmethod
   def low_from_supply(neg: Port[GroundLink], *, current_limits: RangeLike = RangeExpr.ALL) -> DigitalSource:
+    """Sink-only digital source, eg open-drain output"""
     return DigitalSource(
       voltage_out=neg.link().voltage,
       current_limits=current_limits,
@@ -320,6 +321,7 @@ def low_from_supply(neg: Port[GroundLink], *, current_limits: RangeLike = RangeE
 
   @staticmethod
   def high_from_supply(pos: Port[VoltageLink], *, current_limits: RangeLike = RangeExpr.ALL) -> DigitalSource:
+    """Source-only digital source"""
     return DigitalSource(
       voltage_out=pos.link().voltage,
       current_limits=current_limits,

edg/electronics_model/footprint.py

@@ -35,7 +35,7 @@ def gen_block_comp(block_name: str) -> str:
 
 def gen_block_value(block: NetBlock, refdes_mode: RefdesMode) -> str:
     if refdes_mode == RefdesMode.PathnameAsValue:
-        if block.refdes.startswith('TP'):  # test points keep their value
+        if 'TP' in block.refdes:  # test points keep their value
             return f'(value "{block.value}")'
         else:
             pathname = '.'.join(block.path)

edg/jlcparts/JlcPartsBase.py

@@ -95,7 +95,7 @@ def config_root_dir(root_dir: str):
         CapacitorsMultilayer_Ceramic_Capacitors_MLCC___SMDakaSMT.json.gz
         This setting is on a JlcPartsBase-wide basis."""
         assert JlcPartsBase._config_parts_root_dir is None, \
-            f"attempted to reassign configure_root_dir, was {JlcPartsBase._config_parts_root_dir}, new {root_dir}"
+            f"attempted to reassign config_root_dir, was {JlcPartsBase._config_parts_root_dir}, new {root_dir}"
         JlcPartsBase._config_parts_root_dir = root_dir
 
     _JLC_PARTS_FILE_NAMES: ClassVar[List[str]]  # set by subclass
@@ -165,7 +165,7 @@ def _parse_table(cls) -> PartsTable:
 
     @classmethod
     def _row_sort_by(cls, row: PartsTableRow) -> Any:
-        return [not row[cls.BASIC_PART_COL], cls._row_area(row), row[cls.COST_COL]]
+        return [not row[cls.BASIC_PART_COL], cls._row_area(row), super()._row_sort_by(row), row[cls.COST_COL]]
 
     def _row_generate(self, row: PartsTableRow) -> None:
         super()._row_generate(row)