Cleanup from iot devices panel (#418)

Miscellaneous cleanup
- Fix AH1806 pinning
- Remove ADC2 from ESP32C3 (can't be used with WiFi), repin examples to
use other pins
- Change inheritance ordering of parts tables parts to base class (eg
TableInductor) last, logic being that is the most general and the parts
table generic logic (eg, JlcParts) is more specific and should handle
delegating of things like filtering.
- This requires a change in the capacitor structure for parallel
capacitor generation, which must be handled at the top level since it's
not generating a part and needs to skip footprint generation which is
sandwiched between the top-level and capacitor table. Least worst
solution for something that's fundamentally abstraction breaking.
- Deprecate SeriesPowerPptcFuse, use SeriesPowerFuse + refinement
- Deprecate LedDriverSwitchingConverter, setting the ripple as a spec
doesn't really make sense, it should be internal.
- Can't refactor Al8861 to use the new buck converter architecture since
its design guide is weird.
- Fix library viewer tree via categorizations and non_library
annotations

Resolves #415

Author: ducky64

edg/abstract_parts/AbstractCapacitor.py

@@ -264,15 +264,16 @@ def add_derated_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]
     ))
 
   def _row_generate(self, row: PartsTableRow) -> None:
+    """This one is weird. Because this is the last in the class order, this is called last.
+    So the top subclass needs explicit logic to handle parallel capacitors."""
+    super()._row_generate(row)
     if row[self.PARALLEL_COUNT] == 1:
-      super()._row_generate(row)  # creates the footprint
       self.assign(self.actual_derated_capacitance, row[self.DERATED_CAPACITANCE])
     else:
       self.assign(self.actual_part, f"{row[self.PARALLEL_COUNT]}x {row[self.PART_NUMBER_COL]}")
       self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING])
       self.assign(self.actual_capacitance, row[self.PARALLEL_CAPACITANCE])
       self.assign(self.actual_derated_capacitance, row[self.PARALLEL_DERATED_CAPACITANCE])
-      self._make_parallel_footprints(row)
 
   @abstractmethod
   def _make_parallel_footprints(self, row: PartsTableRow) -> None:

edg/abstract_parts/AbstractComparator.py

@@ -1,9 +1,10 @@
 from typing import Mapping
 
+from ..abstract_parts import Analog
 from ..electronics_model import *
 
 
-class Comparator(KiCadInstantiableBlock, Block):
+class Comparator(KiCadInstantiableBlock, Analog):
     """Abstract comparator interface, output goes high when inp > inn."""
     def symbol_pinning(self, symbol_name: str) -> Mapping[str, BasePort]:
         assert symbol_name in ('Simulation_SPICE:OPAMP', 'edg_importable:Opamp')

edg/abstract_parts/AbstractFuse.py

@@ -1,5 +1,7 @@
 from typing import Optional, cast
 
+from deprecated import deprecated
+
 from ..electronics_model import *
 from .Categories import *
 from .PartsTable import PartsTableColumn, PartsTableRow
@@ -132,5 +134,6 @@ def _row_generate(self, row: PartsTableRow) -> None:
     self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING])
 
 
+@deprecated("Use SeriesPowerFuse and a top-level refinement to specify a PPTC fuse")
 class SeriesPowerPptcFuse(SeriesPowerFuse):
   FUSE_TYPE = PptcFuse

edg/abstract_parts/AbstractLedDriver.py

@@ -1,4 +1,5 @@
 from ..abstract_parts import *
+from deprecated import deprecated
 
 
 @abstract_block
@@ -18,6 +19,7 @@ def __init__(self, max_current: RangeLike):
         self.max_current = self.ArgParameter(max_current)
 
 
+@deprecated("ripple should be an internal parameter")
 class LedDriverSwitchingConverter(BlockInterfaceMixin[LedDriver]):
     """LED driver mixin indicating that the LED driver is a switching converter and with a peak-peak ripple limit."""
     @init_in_parent

edg/abstract_parts/Categories.py

@@ -32,6 +32,12 @@ class AnalogFilter(Filter):
   pass
 
 
+@abstract_block
+class RfFilter(AnalogFilter):
+  """RF signal conditioning subcircuit."""
+  pass
+
+
 @abstract_block
 class DigitalFilter(Filter):
   """Digital signal conditioning block."""

edg/abstract_parts/I2cBitBang.py

@@ -6,19 +6,6 @@
 
 class I2cControllerBitBang(BitBangAdapter, Block):
   """Bit-bang adapter for I2C controller"""
-  @staticmethod
-  def digital_external_from_link(link_port: DigitalBidir) -> DigitalBidir:
-    """Creates a DigitalBidir model that is the external-facing port that exports from
-    an internal-facing (link-side) port. The internal-facing port should be ideal.
-    These are basically the semantics of a DigitalBidir bridge.
-    TODO: unify code w/ DigitalBidir bridge?"""
-    return DigitalBidir(
-      voltage_out=link_port.link().voltage, current_draw=link_port.link().current_drawn,
-      voltage_limits=link_port.link().voltage_limits, current_limits=link_port.link().current_limits,
-      output_thresholds=link_port.link().output_thresholds, input_thresholds=link_port.link().input_thresholds,
-      pulldown_capable=link_port.link().pulldown_capable, pullup_capable=link_port.link().pullup_capable
-    )
-
   def __init__(self) -> None:
     super().__init__()
     self.i2c = self.Port(I2cController.empty(), [Output])

edg/abstract_parts/IoController.py

@@ -8,6 +8,7 @@
 from .Categories import ProgrammableController
 
 
+@non_library
 @abstract_block
 class BaseIoController(PinMappable, Block):
   """An abstract IO controller block, that takes power input and provides a grab-bag of common IOs.

edg/abstract_parts/RfNetworks.py

@@ -56,7 +56,7 @@ def _calculate_values(cls, freq: float, z1: complex, z2: complex) -> Tuple[float
             PiLowPassFilter._reactance_to_capacitance(freq, xp)
 
 
-class LLowPassFilterWith2HNotch(AnalogFilter, GeneratorBlock):
+class LLowPassFilterWith2HNotch(GeneratorBlock, RfFilter):
     """L filter for impedance matching for RF with an overlaid second-harmonic LC notch filter.
     The target reactance is given by the L filter.
     Then, the L and C values are from the simultaneous solution of:
@@ -143,7 +143,7 @@ def _calculate_values(cls, freq: float, z1: complex, z2: complex) -> Tuple[float
             PiLowPassFilter._reactance_to_capacitance(freq, net_xs - xs2)
 
 
-class PiLowPassFilter(AnalogFilter, GeneratorBlock):
+class PiLowPassFilter(GeneratorBlock, RfFilter):
     """Passive-typed pi impedance matching network.
     Based on equations from https://www.silabs.com/documents/public/application-notes/an1275-imp-match-for-network-arch.pdf
     and also referencing https://www.electronicdesign.com/technologies/communications/article/21801154/back-to-basics-impedance-matching-part-3

edg/abstract_parts/__init__.py

@@ -9,7 +9,7 @@
 from .Categories import DiscreteComponent, DiscreteSemiconductor, PassiveComponent
 from .Categories import DiscreteApplication
 from .Categories import Analog, OpampApplication
-from .Categories import Filter, AnalogFilter, DigitalFilter
+from .Categories import Filter, AnalogFilter, RfFilter, DigitalFilter
 from .Categories import Microcontroller, Fpga, Memory, RealtimeClock, Radiofrequency
 from .Categories import Interface, AnalogToDigital, DigitalToAnalog, SpeakerDriver, IoExpander, BitBangAdapter
 from .Categories import PowerConditioner, PowerSwitch, MotorDriver, BrushedMotorDriver, BldcDriver

edg/electronics_model/CircuitBlock.py

@@ -91,6 +91,7 @@ def footprint(self, refdes: StringLike, footprint: StringLike, pinning: Mapping[
       self.assign(self.fp_datasheet, '')
 
 
+@non_library
 class WrapperFootprintBlock(FootprintBlock):
   """Block that has a footprint and optional internal contents, but the netlister ignores internal components.
   Useful for, for example, a breakout board where the modelling details are provided by internal chip blocks,