merge

Author: ducky64

edg/BoardTop.py

@@ -78,6 +78,7 @@ def refinements(self) -> Refinements:
         (Resistor, JlcResistor),
         (Capacitor, JlcCapacitor),
         (Inductor, JlcInductor),
+        (AluminumCapacitor, JlcAluminumCapacitor),
         (FerriteBead, JlcFerriteBead),
         (PptcFuse, JlcPptcFuse),
         (ResistorArray, JlcResistorArray),

edg/abstract_parts/AbstractAntenna.py

@@ -7,7 +7,7 @@
 @abstract_block
 class Antenna(Interface, Block):
   @init_in_parent
-  def __init__(self, frequency: RangeLike, impedance: RangeLike = Range.all(), power: RangeLike = (0, 0*Watt)):
+  def __init__(self, frequency: RangeLike, impedance: RangeLike = Range.all(), power: RangeLike = (0, 0)*Watt):
     super().__init__()
 
     self.frequency = self.ArgParameter(frequency)

edg/abstract_parts/AbstractCapacitor.py

@@ -264,15 +264,16 @@ def add_derated_row(row: PartsTableRow) -> Optional[Dict[PartsTableColumn, Any]]
     ))
 
   def _row_generate(self, row: PartsTableRow) -> None:
+    """This one is weird. Because this is the last in the class order, this is called last.
+    So the top subclass needs explicit logic to handle parallel capacitors."""
+    super()._row_generate(row)
     if row[self.PARALLEL_COUNT] == 1:
-      super()._row_generate(row)  # creates the footprint
       self.assign(self.actual_derated_capacitance, row[self.DERATED_CAPACITANCE])
     else:
       self.assign(self.actual_part, f"{row[self.PARALLEL_COUNT]}x {row[self.PART_NUMBER_COL]}")
       self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING])
       self.assign(self.actual_capacitance, row[self.PARALLEL_CAPACITANCE])
       self.assign(self.actual_derated_capacitance, row[self.PARALLEL_DERATED_CAPACITANCE])
-      self._make_parallel_footprints(row)
 
   @abstractmethod
   def _make_parallel_footprints(self, row: PartsTableRow) -> None:

edg/abstract_parts/AbstractComparator.py

@@ -1,10 +1,11 @@
 from typing import Mapping
 
 from .ResistiveDivider import FeedbackVoltageDivider, VoltageDivider
+from ..abstract_parts import Analog
 from ..electronics_model import *
 
 
-class Comparator(KiCadInstantiableBlock, Block):
+class Comparator(KiCadInstantiableBlock, Analog):
     """Abstract comparator interface, output goes high when inp > inn."""
     def symbol_pinning(self, symbol_name: str) -> Mapping[str, BasePort]:
         assert symbol_name in ('Simulation_SPICE:OPAMP', 'edg_importable:Opamp')

edg/abstract_parts/AbstractFuse.py

@@ -1,5 +1,7 @@
 from typing import Optional, cast
 
+from deprecated import deprecated
+
 from ..electronics_model import *
 from .Categories import *
 from .PartsTable import PartsTableColumn, PartsTableRow
@@ -132,5 +134,6 @@ def _row_generate(self, row: PartsTableRow) -> None:
     self.assign(self.actual_voltage_rating, row[self.VOLTAGE_RATING])
 
 
+@deprecated("Use SeriesPowerFuse and a top-level refinement to specify a PPTC fuse")
 class SeriesPowerPptcFuse(SeriesPowerFuse):
   FUSE_TYPE = PptcFuse

edg/abstract_parts/AbstractInductor.py

@@ -1,4 +1,4 @@
-from typing import Dict, Optional, cast
+from typing import Dict, Optional, cast, Any
 
 from ..electronics_model import *
 from .PartsTable import PartsTableColumn, PartsTableRow, ExperimentalUserFnPartsTable
@@ -143,7 +143,6 @@ def __init__(self, *args, **kwargs) -> None:
                          self.experimental_filter_fn)
 
   def _row_filter(self, row: PartsTableRow) -> bool:
-    # TODO eliminate arbitrary DCR limit in favor of exposing max DCR to upper levels
     filter_fn_str = self.get(self.experimental_filter_fn)
     if filter_fn_str:
       filter_fn = ExperimentalUserFnPartsTable.deserialize_fn(filter_fn_str)
@@ -164,6 +163,10 @@ def _row_generate(self, row: PartsTableRow) -> None:
     self.assign(self.actual_frequency_rating, row[self.FREQUENCY_RATING])
     self.assign(self.actual_resistance_dc, row[self.DC_RESISTANCE])
 
+  @classmethod
+  def _row_sort_by(cls, row: PartsTableRow) -> Any:
+    return row[cls.DC_RESISTANCE].center()
+
 
 class SeriesPowerInductor(DiscreteApplication):
   """VoltageSource/Sink-typed series inductor for power filtering"""

edg/abstract_parts/AbstractLedDriver.py

@@ -1,4 +1,5 @@
 from ..abstract_parts import *
+from deprecated import deprecated
 
 
 @abstract_block
@@ -18,6 +19,7 @@ def __init__(self, max_current: RangeLike):
         self.max_current = self.ArgParameter(max_current)
 
 
+@deprecated("ripple should be an internal parameter")
 class LedDriverSwitchingConverter(BlockInterfaceMixin[LedDriver]):
     """LED driver mixin indicating that the LED driver is a switching converter and with a peak-peak ripple limit."""
     @init_in_parent

edg/abstract_parts/Categories.py

@@ -32,6 +32,12 @@ class AnalogFilter(Filter):
   pass
 
 
+@abstract_block
+class RfFilter(AnalogFilter):
+  """RF signal conditioning subcircuit."""
+  pass
+
+
 @abstract_block
 class DigitalFilter(Filter):
   """Digital signal conditioning block."""
@@ -238,7 +244,19 @@ class LightSensor(Sensor):
 
 
 @abstract_block
-class Magnetometer(Sensor):
+class MagneticSensor(Sensor):
+  pass
+
+
+@abstract_block
+class MagneticSwitch(MagneticSensor):
+  """A switch that is activated by a magnetic field, including omnipolar and bipolar devices."""
+  pass
+
+
+@abstract_block
+class Magnetometer(MagneticSensor):
+  """Linear response magnetic field sensor, potentially with multiple axes"""
   pass
 
 

edg/abstract_parts/I2cBitBang.py

@@ -0,0 +1,23 @@
+from typing import cast
+
+from ..electronics_model import *
+from .Categories import *
+
+
+class I2cControllerBitBang(BitBangAdapter, Block):
+  """Bit-bang adapter for I2C controller"""
+  def __init__(self) -> None:
+    super().__init__()
+    self.i2c = self.Port(I2cController.empty(), [Output])
+    self.scl = self.Port(DigitalBidir.empty())
+    self.sda = self.Port(DigitalBidir.empty())
+
+  def contents(self) -> None:
+    super().contents()
+    self.connect(self.i2c.scl, self.scl)
+    self.connect(self.i2c.sda, self.sda)
+
+  def connected_from(self, scl: Port[DigitalLink], sda: Port[DigitalLink]) -> 'I2cControllerBitBang':
+    cast(Block, builder.get_enclosing_block()).connect(scl, self.scl)
+    cast(Block, builder.get_enclosing_block()).connect(sda, self.sda)
+    return self

edg/abstract_parts/IoController.py

@@ -8,6 +8,7 @@
 from .Categories import ProgrammableController
 
 
+@non_library
 @abstract_block
 class BaseIoController(PinMappable, Block):
   """An abstract IO controller block, that takes power input and provides a grab-bag of common IOs.