Carry Save Adder (CSA) – Verilog HDL

📌 Project Description

This repository contains a 5-bit Carry Save Adder (CSA) implemented using Verilog HDL.
The design efficiently adds three 5-bit binary numbers using a carry-save technique and produces a 6-bit final sum.

Carry Save Adders are commonly used in high-speed arithmetic circuits, especially in multipliers, DSP systems, and FPGA-based designs, because they reduce carry propagation delay.

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🧠 Working Principle

Instead of propagating carry bits immediately, the Carry Save Adder:

1. Adds three input bits at each position using Full Adders
2. Produces Sum and Carry separately
3. Shifts carry bits left by one position
4. Uses a Ripple Carry Adder (RCA) in the final stage to compute the result

This approach improves speed compared to conventional ripple carry addition.

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🧩 Module Overview

🔹 Top Module: csa

Inputs

• A[4:0] – First 5-bit operand
• B[4:0] – Second 5-bit operand
• C[4:0] – Third 5-bit operand

Output

• Final_Sum[5:0] – 6-bit sum output (includes carry)

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🔹 Internal Architecture

• Stage 1: Five Full Adders (Carry Save Stage)
• Stage 2: Carry bits shifted left by one bit
• Stage 3: Ripple Carry Adder for final addition

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🧱 Submodules

1️⃣ Full Adder

Used in the carry-save stage to add three bits simultaneously.

Logic

• Sum = A ⊕ B ⊕ Cin
• Carry = (A & B) | (B & Cin) | (Cin & A)

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2️⃣ Ripple Carry Adder

Used in the final stage to add the partial sum and shifted carry.

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📐 Bit Width Details

Signal	Width	Description
A, B, C	5-bit	Input operands
S	5-bit	Partial sum
Carry	5-bit	Carry outputs
Final_Sum	6-bit	Final result

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🚀 Applications

• FPGA arithmetic units
• Digital signal processing (DSP)
• Multipliers and accumulators
• VLSI and computer architecture projects

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🛠 Tools & Simulation

• HDL Language: Verilog
• Simulation: ModelSim / Vivado Simulator
• Synthesis: Xilinx Vivado / Intel Quartus
• Target: FPGA / RTL verification

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✅ Advantages

• Reduced carry propagation delay
• Modular and reusable design
• Simple and readable RTL code

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🔮 Future Improvements

• Parameterized N-bit CSA
• Pipelined CSA architecture
• Testbench with random vectors

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👨‍💻 Author

Developed for Bhavin umatiya.