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calc84maniacadriweb
calc84maniac
authored and
adriweb
committed
Replace pointers to emulated system MMIO with addresses, fix PORT_IOBUS copy-paste error
1 parent 74accd9 commit 1108d9b

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3 files changed

+138
-97
lines changed

3 files changed

+138
-97
lines changed

‎core/arm/armmem.c‎

Lines changed: 112 additions & 95 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,9 @@
1010
#define FLASH_REGION_SIZE (FLASH_SIZE >> 4)
1111
#define FLASH_ROW_SIZE (FLASH_PAGE_SIZE << 2)
1212

13+
#define PORT_PMUX_COUNT 16
14+
#define PORT_PINCFG_COUNT 32
15+
1316
#define ARM_SERCOM_SLEEP 4
1417

1518
static uint32_t bitreverse(uint32_t x, uint8_t bits) {
@@ -495,9 +498,9 @@ static uint32_t arm_mem_load_any(arm_t *arm, uint32_t addr) {
495498
case PORT_WRCONFIG_OFFSET >> 2:
496499
return PORT_WRCONFIG_RESETVALUE;
497500
default:
498-
if (addr - (uint32_t)&PORT->Group->PMUX < sizeof(PORT->Group->PMUX)) {
501+
if (addr - (uint32_t)(PORT + PORT_PMUX_OFFSET) < (PORT_PMUX_COUNT << 2)) {
499502
return PORT_PMUX_RESETVALUE;
500-
} else if (addr - (uint32_t)&PORT->Group->PINCFG < sizeof(PORT->Group->PINCFG)) {
503+
} else if (addr - (uint32_t)(PORT + PORT_PINCFG_OFFSET) < (PORT_PINCFG_COUNT << 2)) {
501504
return PORT_PINCFG_RESETVALUE;
502505
}
503506
break;
@@ -689,9 +692,9 @@ static uint32_t arm_mem_load_any(arm_t *arm, uint32_t addr) {
689692
case PORT_WRCONFIG_OFFSET >> 2:
690693
return PORT_WRCONFIG_RESETVALUE;
691694
default:
692-
if (addr - (uint32_t)&PORT->Group->PMUX < sizeof(PORT->Group->PMUX)) {
695+
if (addr - (uint32_t)(PORT_IOBUS + PORT_PMUX_OFFSET) < (PORT_PMUX_COUNT << 2)) {
693696
return PORT_PMUX_RESETVALUE;
694-
} else if (addr - (uint32_t)&PORT->Group->PINCFG < sizeof(PORT->Group->PINCFG)) {
697+
} else if (addr - (uint32_t)(PORT_IOBUS + PORT_PINCFG_OFFSET) < (PORT_PINCFG_COUNT << 2)) {
695698
return PORT_PINCFG_RESETVALUE;
696699
}
697700
break;
@@ -730,52 +733,57 @@ uint32_t arm_mem_load_word(arm_t *arm, uint32_t addr) {
730733
} else if (unlikely(addr < SysTick_BASE)) {
731734
} else if (unlikely(addr < NVIC_BASE)) {
732735
arm_systick_t *systick = &arm->cpu.systick;
733-
if (addr == (uint32_t)&SysTick->CTRL) {
734-
val = systick->ctrl;
735-
systick->ctrl &= ~SysTick_CTRL_COUNTFLAG_Msk;
736-
return val;
737-
} else if (addr == (uint32_t)&SysTick->LOAD) {
738-
return systick->load;
739-
} else if (addr == (uint32_t)&SysTick->VAL) {
740-
return systick->val;
741-
} else if (addr == (uint32_t)&SysTick->CALIB) {
736+
switch (addr - SysTick_BASE) {
737+
case 0x000: // CTRL
738+
val = systick->ctrl;
739+
systick->ctrl &= ~SysTick_CTRL_COUNTFLAG_Msk;
740+
return val;
741+
case 0x004: // LOAD
742+
return systick->load;
743+
case 0x008: // VAL
744+
return systick->val;
745+
case 0x00C: // CALIB
746+
break;
747+
default:
748+
break;
742749
}
743750
} else if (unlikely(addr < SCB_BASE)) {
744751
arm_nvic_t *nvic = &arm->cpu.nvic;
745-
if (addr == (uint32_t)&NVIC->ISER[0] ||
746-
addr == (uint32_t)&NVIC->ICER[0]) {
752+
if (addr == NVIC_BASE + 0x000 || // ISER[0]
753+
addr == NVIC_BASE + 0x080) { // ICER[0]
747754
return nvic->ier;
748-
} else if (addr == (uint32_t)&NVIC->ISPR[0] ||
749-
addr == (uint32_t)&NVIC->ICPR[0]) {
755+
} else if (addr == NVIC_BASE + 0x100 || // ISPR[0]
756+
addr == NVIC_BASE + 0x180) { // ICPR[0]
750757
return nvic->ipr;
751-
} else if (addr >= (uint32_t)&NVIC->IP[0] &&
752-
addr <= (uint32_t)&NVIC->IP[7]) {
758+
} else if (addr >= NVIC_BASE + 0x300 &&
759+
addr < NVIC_BASE + 0x320) { // IP[0] - IP[7]
753760
return nvic->ip[addr >> 2 & 7];
754761
}
755762
} else {
756763
arm_scb_t *scb = &arm->cpu.scb;
757-
if (addr == (uint32_t)&SCB->CPUID) {
758-
return 'A' << SCB_CPUID_IMPLEMENTER_Pos |
759-
0 << SCB_CPUID_VARIANT_Pos |
760-
12 << SCB_CPUID_ARCHITECTURE_Pos |
761-
28 << SCB_CPUID_PARTNO_Pos |
762-
6 << SCB_CPUID_REVISION_Pos;
763-
} else if (addr == (uint32_t)&SCB->ICSR) {
764-
return scb->icsr;
765-
} else if (addr == (uint32_t)&SCB->VTOR) {
766-
return scb->vtor;
767-
} else if (addr == (uint32_t)&SCB->AIRCR) {
768-
return 0;
769-
} else if (addr == (uint32_t)&SCB->CCR) {
770-
return SCB_CCR_STKALIGN_Msk |
771-
SCB_CCR_UNALIGN_TRP_Msk;
772-
} else if (addr == (uint32_t)&SCB->SHP[0]) {
773-
return scb->shp[0];
774-
} else if (addr == (uint32_t)&SCB->SHP[1]) {
775-
return scb->shp[1];
776-
} else if (addr == (uint32_t)&SCB->SHCSR) {
777-
return (scb->icsr & SCB_ICSR_PENDSVSET_Msk) >>
778-
SCB_ICSR_PENDSVSET_Pos << SCB_SHCSR_SVCALLPENDED_Pos;
764+
switch (addr - SCB_BASE) {
765+
case 0x000: // CPUID
766+
return 'A' << SCB_CPUID_IMPLEMENTER_Pos |
767+
0 << SCB_CPUID_VARIANT_Pos |
768+
12 << SCB_CPUID_ARCHITECTURE_Pos |
769+
28 << SCB_CPUID_PARTNO_Pos |
770+
6 << SCB_CPUID_REVISION_Pos;
771+
case 0x004: // ICSR
772+
return scb->icsr;
773+
case 0x008: // VTOR
774+
return scb->vtor;
775+
case 0x00C: // AIRCR
776+
return 0;
777+
case 0x014: // CCR
778+
return SCB_CCR_STKALIGN_Msk |
779+
SCB_CCR_UNALIGN_TRP_Msk;
780+
case 0x01C: // SHP[0]
781+
return scb->shp[0];
782+
case 0x020: // SHP[1]
783+
return scb->shp[1];
784+
case 0x024: // SHCSR
785+
return (scb->icsr & SCB_ICSR_PENDSVSET_Msk) >>
786+
SCB_ICSR_PENDSVSET_Pos << SCB_SHCSR_SVCALLPENDED_Pos;
779787
}
780788
}
781789
if (arm->debug) {
@@ -1053,9 +1061,9 @@ static void arm_mem_store_any(arm_t *arm, uint32_t val, uint32_t mask, uint32_t
10531061
case PORT_WRCONFIG_OFFSET >> 2:
10541062
return;
10551063
default:
1056-
if (addr - (uint32_t)&PORT->Group->PMUX < sizeof(PORT->Group->PMUX)) {
1064+
if (addr - (uint32_t)(PORT + PORT_PMUX_OFFSET) < (PORT_PMUX_COUNT << 2)) {
10571065
return;
1058-
} else if (addr - (uint32_t)&PORT->Group->PINCFG < sizeof(PORT->Group->PINCFG)) {
1066+
} else if (addr - (uint32_t)(PORT + PORT_PINCFG_OFFSET) < (PORT_PINCFG_COUNT << 2)) {
10591067
return;
10601068
}
10611069
break;
@@ -1091,7 +1099,7 @@ static void arm_mem_store_any(arm_t *arm, uint32_t val, uint32_t mask, uint32_t
10911099
}
10921100
} else { // SBMATRIX
10931101
switch (addr) {
1094-
case (uint32_t)&REG_SBMATRIX_SFR4:
1102+
case (uint32_t)REG_SBMATRIX_SFR4:
10951103
return;
10961104
}
10971105
}
@@ -1332,9 +1340,9 @@ static void arm_mem_store_any(arm_t *arm, uint32_t val, uint32_t mask, uint32_t
13321340
case PORT_WRCONFIG_OFFSET >> 2:
13331341
return;
13341342
default:
1335-
if (addr - (uint32_t)&PORT->Group->PMUX < sizeof(PORT->Group->PMUX)) {
1343+
if (addr - (uint32_t)(PORT_IOBUS + PORT_PMUX_OFFSET) < (PORT_PMUX_COUNT << 2)) {
13361344
return;
1337-
} else if (addr - (uint32_t)&PORT->Group->PINCFG < sizeof(PORT->Group->PINCFG)) {
1345+
} else if (addr - (uint32_t)(PORT_IOBUS + PORT_PINCFG_OFFSET) < (PORT_PINCFG_COUNT << 2)) {
13381346
return;
13391347
}
13401348
break;
@@ -1372,71 +1380,80 @@ void arm_mem_store_word(arm_t *arm, uint32_t val, uint32_t addr) {
13721380
} else if (unlikely(addr < SysTick_BASE)) {
13731381
} else if (unlikely(addr < NVIC_BASE)) {
13741382
arm_systick_t *systick = &arm->cpu.systick;
1375-
if (addr == (uint32_t)&SysTick->CTRL) {
1376-
systick->ctrl = (systick->ctrl & SysTick_CTRL_COUNTFLAG_Msk) |
1377-
(val & (SysTick_CTRL_CLKSOURCE_Msk |
1378-
SysTick_CTRL_TICKINT_Msk |
1379-
SysTick_CTRL_ENABLE_Msk));
1380-
return;
1381-
} else if (addr == (uint32_t)&SysTick->LOAD) {
1382-
systick->load = val & SysTick_LOAD_RELOAD_Msk;
1383-
return;
1384-
} else if (addr == (uint32_t)&SysTick->VAL) {
1385-
systick->ctrl &= ~SysTick_CTRL_COUNTFLAG_Msk;
1386-
systick->val = 0;
1387-
return;
1388-
} else if (addr == (uint32_t)&SysTick->CALIB) {
1383+
switch (addr - SysTick_BASE) {
1384+
case 0x000: // CTRL
1385+
systick->ctrl = (systick->ctrl & SysTick_CTRL_COUNTFLAG_Msk) |
1386+
(val & (SysTick_CTRL_CLKSOURCE_Msk |
1387+
SysTick_CTRL_TICKINT_Msk |
1388+
SysTick_CTRL_ENABLE_Msk));
1389+
return;
1390+
case 0x004: // LOAD
1391+
systick->load = val & SysTick_LOAD_RELOAD_Msk;
1392+
return;
1393+
case 0x008: // VAL
1394+
systick->ctrl &= ~SysTick_CTRL_COUNTFLAG_Msk;
1395+
systick->val = 0;
1396+
return;
1397+
case 0x00C: // CALIB
1398+
break;
1399+
default:
1400+
break;
13891401
}
13901402
} else if (unlikely(addr < SCB_BASE)) {
13911403
arm_nvic_t *nvic = &arm->cpu.nvic;
1392-
if (addr == (uint32_t)&NVIC->ISER[0]) {
1404+
if (addr == NVIC_BASE + 0x000) { // ISER[0]
13931405
nvic->ier |= val;
13941406
return;
1395-
} else if (addr == (uint32_t)&NVIC->ICER[0]) {
1407+
} else if (addr == NVIC_BASE + 0x080) { // ICER[0]
13961408
nvic->ier &= ~val;
13971409
return;
1398-
} else if (addr == (uint32_t)&NVIC->ISPR[0]) {
1410+
} else if (addr == NVIC_BASE + 0x100) { // ISPR[0]
13991411
nvic->ipr |= val;
14001412
return;
1401-
} else if (addr == (uint32_t)&NVIC->ICPR[0]) {
1413+
} else if (addr == NVIC_BASE + 0x180) { // ICPR[0]
14021414
nvic->ipr &= ~val;
14031415
return;
1404-
} else if (addr >= (uint32_t)&NVIC->IP[0] && addr <= (uint32_t)&NVIC->IP[7]) {
1416+
} else if (addr >= NVIC_BASE + 0x300 &&
1417+
addr < NVIC_BASE + 0x320) { // IP[0] - IP[7]
14051418
nvic->ip[addr >> 2 & 7] = val & UINT32_C(0xC0C0C0C0);
14061419
return;
14071420
}
14081421
} else {
14091422
arm_scb_t *scb = &arm->cpu.scb;
1410-
if (addr == (uint32_t)&SCB->ICSR) {
1411-
if (val & SCB_ICSR_NMIPENDSET_Msk) {
1412-
scb->icsr |= SCB_ICSR_NMIPENDSET_Msk;
1413-
}
1414-
if (val & SCB_ICSR_PENDSVSET_Msk) {
1415-
scb->icsr |= SCB_ICSR_PENDSVSET_Msk;
1416-
} else if (val & SCB_ICSR_PENDSVCLR_Msk) {
1417-
scb->icsr &= ~SCB_ICSR_PENDSVSET_Msk;
1418-
}
1419-
if (val & SCB_ICSR_PENDSTSET_Msk) {
1420-
scb->icsr |= SCB_ICSR_PENDSTSET_Msk;
1421-
} else if (val & SCB_ICSR_PENDSTCLR_Msk) {
1422-
scb->icsr &= ~SCB_ICSR_PENDSTSET_Msk;
1423-
}
1424-
return;
1425-
} else if (addr == (uint32_t)&SCB->VTOR) {
1426-
scb->vtor = val & SCB_VTOR_TBLOFF_Msk;
1427-
return;
1428-
} else if (addr == (uint32_t)&SCB->SHP[0]) {
1429-
scb->shp[0] = val & UINT32_C(0xC0000000);
1430-
return;
1431-
} else if (addr == (uint32_t)&SCB->SHP[1]) {
1432-
scb->shp[1] = val & UINT32_C(0xC0C00000);
1433-
return;
1434-
} else if (addr == (uint32_t)&SCB->SHCSR) {
1435-
if (val & SCB_SHCSR_SVCALLPENDED_Msk) {
1436-
scb->icsr |= SCB_ICSR_PENDSVSET_Msk;
1437-
} else {
1438-
scb->icsr &= ~SCB_ICSR_PENDSVSET_Msk;
1439-
}
1423+
switch (addr - SCB_BASE) {
1424+
case 0x004: // ICSR
1425+
if (val & SCB_ICSR_NMIPENDSET_Msk) {
1426+
scb->icsr |= SCB_ICSR_NMIPENDSET_Msk;
1427+
}
1428+
if (val & SCB_ICSR_PENDSVSET_Msk) {
1429+
scb->icsr |= SCB_ICSR_PENDSVSET_Msk;
1430+
} else if (val & SCB_ICSR_PENDSVCLR_Msk) {
1431+
scb->icsr &= ~SCB_ICSR_PENDSVSET_Msk;
1432+
}
1433+
if (val & SCB_ICSR_PENDSTSET_Msk) {
1434+
scb->icsr |= SCB_ICSR_PENDSTSET_Msk;
1435+
} else if (val & SCB_ICSR_PENDSTCLR_Msk) {
1436+
scb->icsr &= ~SCB_ICSR_PENDSTSET_Msk;
1437+
}
1438+
return;
1439+
case 0x008: // VTOR
1440+
scb->vtor = val & SCB_VTOR_TBLOFF_Msk;
1441+
return;
1442+
case 0x01C: // SHP[0]
1443+
scb->shp[0] = val & UINT32_C(0xC0000000);
1444+
return;
1445+
case 0x020: // SHP[1]
1446+
scb->shp[1] = val & UINT32_C(0xC0C00000);
1447+
return;
1448+
case 0x024: // SHCSR
1449+
if (val & SCB_SHCSR_SVCALLPENDED_Msk) {
1450+
scb->icsr |= SCB_ICSR_PENDSVSET_Msk;
1451+
} else {
1452+
scb->icsr &= ~SCB_ICSR_PENDSVSET_Msk;
1453+
}
1454+
return;
1455+
default:
1456+
break;
14401457
}
14411458
}
14421459
if (arm->debug) {

‎core/arm/samd21a/include/instance/sbmatrix.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
#define _SAMD21_SBMATRIX_INSTANCE_
3232

3333
/* ========== Register definition for SBMATRIX peripheral ========== */
34-
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
34+
#if (defined(NO_VOLATILE_CONST_IO) || defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3535
#define REG_SBMATRIX_PRAS0 (0x41007080) /**< \brief (SBMATRIX) Priority A for Slave 0 */
3636
#define REG_SBMATRIX_PRBS0 (0x41007084) /**< \brief (SBMATRIX) Priority B for Slave 0 */
3737
#define REG_SBMATRIX_PRAS1 (0x41007088) /**< \brief (SBMATRIX) Priority A for Slave 1 */

‎core/arm/samd21a/include/samd21e18a.h‎

Lines changed: 25 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -369,7 +369,7 @@ void I2S_Handler ( void );
369369
/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */
370370
/*@{*/
371371

372-
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
372+
#if defined(NO_VOLATILE_CONST_IO) || defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
373373
#define AC (0x42004400) /**< \brief (AC) APB Base Address */
374374
#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */
375375
#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */
@@ -410,6 +410,30 @@ void I2S_Handler ( void );
410410
#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */
411411
#define USB (0x41005000) /**< \brief (USB) APB Base Address */
412412
#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */
413+
414+
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
415+
#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
416+
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
417+
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
418+
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
419+
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
420+
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
421+
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
422+
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
423+
#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
424+
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
425+
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
426+
#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
427+
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
428+
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
429+
#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
430+
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
431+
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
432+
#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
433+
#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
434+
#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
435+
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
436+
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
413437
#else
414438
#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
415439
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */

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