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[CHERI] Do not expand memory intrinsics in pre-isel-intrinsic-lowering
Since 3c84819 building with -fno-builtin will expand memory intrinsics in IR instead of going to the default SelectionDAG IR. This lowering does not consider capabilities so will result in IR that does not preserve tag bits. Disable the pass if the datalayout contains capability types to work around this problem. Filed CTSRD-CHERI#753 as a tracking bug to enable it with fixes in the future.
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‎llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -201,6 +201,10 @@ bool PreISelIntrinsicLowering::expandMemIntrinsicUses(Function &F) const {
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auto *Memcpy = cast<MemCpyInst>(Inst);
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Function *ParentFunc = Memcpy->getFunction();
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const TargetTransformInfo &TTI = LookupTTI(*ParentFunc);
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// TODO: we can't expand memcpy for CHERI targets yet.
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// See https://github.com/CTSRD-CHERI/llvm-project/issues/753
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if (Memcpy->getModule()->getDataLayout().hasCheriCapabilities())
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break;
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if (shouldExpandMemIntrinsicWithSize(Memcpy->getLength(), TTI)) {
205209
if (UseMemIntrinsicLibFunc &&
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LookupLibInfo(*ParentFunc).has(LibFunc_memcpy))
@@ -217,6 +221,10 @@ bool PreISelIntrinsicLowering::expandMemIntrinsicUses(Function &F) const {
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auto *Memmove = cast<MemMoveInst>(Inst);
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Function *ParentFunc = Memmove->getFunction();
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const TargetTransformInfo &TTI = LookupTTI(*ParentFunc);
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// TODO: we can't expand memmove for CHERI targets yet.
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// See https://github.com/CTSRD-CHERI/llvm-project/issues/753
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if (Memmove->getModule()->getDataLayout().hasCheriCapabilities())
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break;
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if (shouldExpandMemIntrinsicWithSize(Memmove->getLength(), TTI)) {
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if (UseMemIntrinsicLibFunc &&
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LookupLibInfo(*ParentFunc).has(LibFunc_memmove))

‎llvm/test/CodeGen/CHERI-Generic/lower-mem-intrinsics.ll‎

Lines changed: 186 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,186 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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;; Check that we don't expand for CHERI targets (yet): https://github.com/CTSRD-CHERI/llvm-project/issues/753
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; RUN: opt -S -mtriple=riscv64 -pre-isel-intrinsic-lowering -mem-intrinsic-expand-size=0 --print-before-all < %s | FileCheck %s --check-prefixes=CHECK,RISCV
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; RUN: opt -S -mtriple=riscv64 -data-layout="pf200:128:128:128:64" -mem-intrinsic-expand-size=0 -pre-isel-intrinsic-lowering < %s | FileCheck %s --check-prefixes=CHECK,HYBRID
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declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1)
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declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1)
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declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1)
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define void @call_memset(ptr align 16 %dst) #0 {
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; CHECK-LABEL: @call_memset(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]]
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; CHECK: loadstoreloop:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[TMP2:%.*]], [[LOADSTORELOOP]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[TMP0]]
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; CHECK-NEXT: store i8 0, ptr [[TMP1]], align 1
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; CHECK-NEXT: [[TMP2]] = add i64 [[TMP0]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 40
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; CHECK-NEXT: br i1 [[TMP3]], label [[LOADSTORELOOP]], label [[SPLIT]]
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; CHECK: split:
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; CHECK-NEXT: ret void
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;
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entry:
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call void @llvm.memset.p0.i64(ptr align 16 %dst, i8 0, i64 40, i1 false)
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ret void
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}
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define void @call_memset_variable(ptr align 16 %dst, i64 %len) #0 {
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; CHECK-LABEL: @call_memset_variable(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 0, [[LEN:%.*]]
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; CHECK-NEXT: br i1 [[TMP0]], label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]]
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; CHECK: loadstoreloop:
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; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[TMP1]]
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; CHECK-NEXT: store i8 0, ptr [[TMP2]], align 1
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; CHECK-NEXT: [[TMP3]] = add i64 [[TMP1]], 1
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; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], [[LEN]]
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; CHECK-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]]
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; CHECK: split:
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; CHECK-NEXT: ret void
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;
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entry:
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call void @llvm.memset.p0.i64(ptr align 16 %dst, i8 0, i64 %len, i1 false)
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ret void
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}
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define void @call_memcpy(ptr align 16 %dst, ptr align 16 %src) #0 {
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; RISCV-LABEL: @call_memcpy(
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; RISCV-NEXT: entry:
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; RISCV-NEXT: br label [[LOAD_STORE_LOOP:%.*]]
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; RISCV: load-store-loop:
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; RISCV-NEXT: [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[TMP3:%.*]], [[LOAD_STORE_LOOP]] ]
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; RISCV-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[LOOP_INDEX]]
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; RISCV-NEXT: [[TMP1:%.*]] = load i8, ptr [[TMP0]], align 1
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; RISCV-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[LOOP_INDEX]]
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; RISCV-NEXT: store i8 [[TMP1]], ptr [[TMP2]], align 1
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; RISCV-NEXT: [[TMP3]] = add i64 [[LOOP_INDEX]], 1
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; RISCV-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 40
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; RISCV-NEXT: br i1 [[TMP4]], label [[LOAD_STORE_LOOP]], label [[MEMCPY_SPLIT:%.*]]
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; RISCV: memcpy-split:
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; RISCV-NEXT: ret void
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;
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; HYBRID-LABEL: @call_memcpy(
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; HYBRID-NEXT: entry:
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; HYBRID-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[DST:%.*]], ptr align 16 [[SRC:%.*]], i64 40, i1 false)
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; HYBRID-NEXT: ret void
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;
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entry:
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call void @llvm.memcpy.p0.p0.i64(ptr align 16 %dst, ptr align 16 %src, i64 40, i1 false)
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ret void
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}
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define void @call_memcpy_variable(ptr align 16 %dst, ptr align 16 %src, i64 %len) #0 {
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; RISCV-LABEL: @call_memcpy_variable(
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; RISCV-NEXT: entry:
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; RISCV-NEXT: [[TMP0:%.*]] = icmp ne i64 [[LEN:%.*]], 0
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; RISCV-NEXT: br i1 [[TMP0]], label [[LOOP_MEMCPY_EXPANSION:%.*]], label [[POST_LOOP_MEMCPY_EXPANSION:%.*]]
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; RISCV: loop-memcpy-expansion:
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; RISCV-NEXT: [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[TMP4:%.*]], [[LOOP_MEMCPY_EXPANSION]] ]
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; RISCV-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC:%.*]], i64 [[LOOP_INDEX]]
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; RISCV-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
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; RISCV-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[DST:%.*]], i64 [[LOOP_INDEX]]
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; RISCV-NEXT: store i8 [[TMP2]], ptr [[TMP3]], align 1
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; RISCV-NEXT: [[TMP4]] = add i64 [[LOOP_INDEX]], 1
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; RISCV-NEXT: [[TMP5:%.*]] = icmp ult i64 [[TMP4]], [[LEN]]
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; RISCV-NEXT: br i1 [[TMP5]], label [[LOOP_MEMCPY_EXPANSION]], label [[POST_LOOP_MEMCPY_EXPANSION]]
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; RISCV: post-loop-memcpy-expansion:
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; RISCV-NEXT: ret void
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;
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; HYBRID-LABEL: @call_memcpy_variable(
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; HYBRID-NEXT: entry:
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; HYBRID-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[DST:%.*]], ptr align 16 [[SRC:%.*]], i64 [[LEN:%.*]], i1 false)
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; HYBRID-NEXT: ret void
96+
;
97+
entry:
98+
call void @llvm.memcpy.p0.p0.i64(ptr align 16 %dst, ptr align 16 %src, i64 %len, i1 false)
99+
ret void
100+
}
101+
102+
define void @call_memmove(ptr align 16 %dst, ptr align 16 %src) #0 {
103+
; RISCV-LABEL: @call_memmove(
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; RISCV-NEXT: entry:
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; RISCV-NEXT: [[COMPARE_SRC_DST:%.*]] = icmp ult ptr [[SRC:%.*]], [[DST:%.*]]
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; RISCV-NEXT: [[COMPARE_N_TO_0:%.*]] = icmp eq i64 40, 0
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; RISCV-NEXT: br i1 [[COMPARE_SRC_DST]], label [[COPY_BACKWARDS:%.*]], label [[COPY_FORWARD:%.*]]
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; RISCV: copy_backwards:
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; RISCV-NEXT: br i1 [[COMPARE_N_TO_0]], label [[MEMMOVE_DONE:%.*]], label [[COPY_BACKWARDS_LOOP:%.*]]
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; RISCV: copy_backwards_loop:
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; RISCV-NEXT: [[TMP0:%.*]] = phi i64 [ [[INDEX_PTR:%.*]], [[COPY_BACKWARDS_LOOP]] ], [ 40, [[COPY_BACKWARDS]] ]
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; RISCV-NEXT: [[INDEX_PTR]] = sub i64 [[TMP0]], 1
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; RISCV-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX_PTR]]
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; RISCV-NEXT: [[ELEMENT:%.*]] = load i8, ptr [[TMP1]], align 1
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; RISCV-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX_PTR]]
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; RISCV-NEXT: store i8 [[ELEMENT]], ptr [[TMP2]], align 1
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; RISCV-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_PTR]], 0
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; RISCV-NEXT: br i1 [[TMP3]], label [[MEMMOVE_DONE]], label [[COPY_BACKWARDS_LOOP]]
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; RISCV: copy_forward:
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; RISCV-NEXT: br i1 [[COMPARE_N_TO_0]], label [[MEMMOVE_DONE]], label [[COPY_FORWARD_LOOP:%.*]]
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; RISCV: copy_forward_loop:
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; RISCV-NEXT: [[INDEX_PTR1:%.*]] = phi i64 [ [[INDEX_INCREMENT:%.*]], [[COPY_FORWARD_LOOP]] ], [ 0, [[COPY_FORWARD]] ]
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; RISCV-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX_PTR1]]
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; RISCV-NEXT: [[ELEMENT2:%.*]] = load i8, ptr [[TMP4]], align 1
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; RISCV-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX_PTR1]]
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; RISCV-NEXT: store i8 [[ELEMENT2]], ptr [[TMP5]], align 1
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; RISCV-NEXT: [[INDEX_INCREMENT]] = add i64 [[INDEX_PTR1]], 1
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; RISCV-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_INCREMENT]], 40
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; RISCV-NEXT: br i1 [[TMP6]], label [[MEMMOVE_DONE]], label [[COPY_FORWARD_LOOP]]
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; RISCV: memmove_done:
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; RISCV-NEXT: ret void
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;
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; HYBRID-LABEL: @call_memmove(
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; HYBRID-NEXT: entry:
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; HYBRID-NEXT: call void @llvm.memmove.p0.p0.i64(ptr align 16 [[DST:%.*]], ptr align 16 [[SRC:%.*]], i64 40, i1 false)
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; HYBRID-NEXT: ret void
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;
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entry:
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call void @llvm.memmove.p0.p0.i64(ptr align 16 %dst, ptr align 16 %src, i64 40, i1 false)
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ret void
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}
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define void @call_memmove_variable(ptr align 16 %dst, ptr align 16 %src, i64 %len) #0 {
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; RISCV-LABEL: @call_memmove_variable(
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; RISCV-NEXT: entry:
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; RISCV-NEXT: [[COMPARE_SRC_DST:%.*]] = icmp ult ptr [[SRC:%.*]], [[DST:%.*]]
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; RISCV-NEXT: [[COMPARE_N_TO_0:%.*]] = icmp eq i64 [[LEN:%.*]], 0
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; RISCV-NEXT: br i1 [[COMPARE_SRC_DST]], label [[COPY_BACKWARDS:%.*]], label [[COPY_FORWARD:%.*]]
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; RISCV: copy_backwards:
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; RISCV-NEXT: br i1 [[COMPARE_N_TO_0]], label [[MEMMOVE_DONE:%.*]], label [[COPY_BACKWARDS_LOOP:%.*]]
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; RISCV: copy_backwards_loop:
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; RISCV-NEXT: [[TMP0:%.*]] = phi i64 [ [[INDEX_PTR:%.*]], [[COPY_BACKWARDS_LOOP]] ], [ [[LEN]], [[COPY_BACKWARDS]] ]
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; RISCV-NEXT: [[INDEX_PTR]] = sub i64 [[TMP0]], 1
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; RISCV-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX_PTR]]
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; RISCV-NEXT: [[ELEMENT:%.*]] = load i8, ptr [[TMP1]], align 1
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; RISCV-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX_PTR]]
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; RISCV-NEXT: store i8 [[ELEMENT]], ptr [[TMP2]], align 1
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; RISCV-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_PTR]], 0
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; RISCV-NEXT: br i1 [[TMP3]], label [[MEMMOVE_DONE]], label [[COPY_BACKWARDS_LOOP]]
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; RISCV: copy_forward:
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; RISCV-NEXT: br i1 [[COMPARE_N_TO_0]], label [[MEMMOVE_DONE]], label [[COPY_FORWARD_LOOP:%.*]]
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; RISCV: copy_forward_loop:
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; RISCV-NEXT: [[INDEX_PTR1:%.*]] = phi i64 [ [[INDEX_INCREMENT:%.*]], [[COPY_FORWARD_LOOP]] ], [ 0, [[COPY_FORWARD]] ]
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; RISCV-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX_PTR1]]
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; RISCV-NEXT: [[ELEMENT2:%.*]] = load i8, ptr [[TMP4]], align 1
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; RISCV-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX_PTR1]]
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; RISCV-NEXT: store i8 [[ELEMENT2]], ptr [[TMP5]], align 1
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; RISCV-NEXT: [[INDEX_INCREMENT]] = add i64 [[INDEX_PTR1]], 1
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; RISCV-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_INCREMENT]], [[LEN]]
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; RISCV-NEXT: br i1 [[TMP6]], label [[MEMMOVE_DONE]], label [[COPY_FORWARD_LOOP]]
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; RISCV: memmove_done:
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; RISCV-NEXT: ret void
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;
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; HYBRID-LABEL: @call_memmove_variable(
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; HYBRID-NEXT: entry:
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; HYBRID-NEXT: call void @llvm.memmove.p0.p0.i64(ptr align 16 [[DST:%.*]], ptr align 16 [[SRC:%.*]], i64 [[LEN:%.*]], i1 false)
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; HYBRID-NEXT: ret void
178+
;
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entry:
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call void @llvm.memmove.p0.p0.i64(ptr align 16 %dst, ptr align 16 %src, i64 %len, i1 false)
181+
ret void
182+
}
183+
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;; We need the "no-builtins" attribute here otherwise the IR lowering pass will
185+
;; be skipped since it assumes the libfunc can be called.
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attributes #0 = { nounwind "no-builtins" }

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