[CHERIoT] Clean up direct references to the "cheriot" CPU name in favor of FeatureVendorXCheriot

clang/test/Driver/print-supported-extensions-riscv.c

@@ -151,7 +151,7 @@
 // CHECK-NEXT:     svpbmt               1.0       'Svpbmt' (Page-Based Memory Types)
 // CHECK-NEXT:     svvptc               1.0       'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
 // CHECK-NEXT:     xcheri               0.0       'XCheri' (Implements CHERI extension)
-// CHECK-NEXT:     xcheriot1            1.0       'XCheriot1' (Implements Cheriot1 extension)
+// CHECK-NEXT:     xcheriot             1.0       'XCheriot' (Implements XCheriot extension)
 // CHECK-NEXT:     xcvalu               1.0       'XCValu' (CORE-V ALU Operations)
 // CHECK-NEXT:     xcvbi                1.0       'XCVbi' (CORE-V Immediate Branching)
 // CHECK-NEXT:     xcvbitmanip          1.0       'XCVbitmanip' (CORE-V Bit Manipulation)

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -1827,8 +1827,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
         "%cheri_compartment_cgprel_hi modifier or "
         "an integer in the range");
   case Match_InvalidUImm20AUIPC:
-    // FIXME: This should be keyed off an Xcheriot feature, not a CPU name.
-    if (getSTI().getCPU() == "cheriot")
+    if (getSTI().hasFeature(RISCV::FeatureVendorXCheriot))
       return generateImmOutOfRangeError(
           Operands, ErrorInfo, 0, (1 << 20) - 1,
           "operand must be a symbol with a "

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

@@ -145,11 +145,11 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
   if (FeatureBits[RISCV::Feature32Bit] &&
       FeatureBits[RISCV::Feature64Bit])
     report_fatal_error("RV32 and RV64 can't be combined");
-  if (FeatureBits[RISCV::FeatureVendorXCheriot1]) {
+  if (FeatureBits[RISCV::FeatureVendorXCheriot]) {
     if (!FeatureBits[RISCV::FeatureVendorXCheri])
-      report_fatal_error("XCheriotV1 extension requires XCheri extension");
+      report_fatal_error("XCheriot extension requires XCheri extension");
     if (!FeatureBits[RISCV::FeatureCapMode])
-      report_fatal_error("XCheriotV1 extension requires CapMode");
+      report_fatal_error("XCheriot extension requires CapMode");
   }
 }
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVCompressedCap.cpp

@@ -18,7 +18,7 @@ namespace RISCVCompressedCap {
 
 static inline CompressedCapability::CapabilityFormat
 GetCapabilitySize(const MCSubtargetInfo &STI) {
-  if (STI.getCPU() == "cheriot")
+  if (STI.hasFeature(RISCV::FeatureVendorXCheriot))
     return CompressedCapability::Cheriot64;
 
   bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

@@ -108,8 +108,9 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
       return ELF::R_RISCV_CHERI_CJAL;
     case RISCV::fixup_riscv_ccall: {
       const auto *STI = Ctx.getSubtargetInfo();
-      if (STI->getCPU() == "cheriot" || STI->getTargetTriple().getSubArch() ==
-                                            Triple::RISCV32SubArch_cheriot_v1)
+      if (STI->hasFeature(RISCV::FeatureVendorXCheriot) ||
+          STI->getTargetTriple().getSubArch() ==
+              Triple::RISCV32SubArch_cheriot_v1)
         return ELF::R_RISCV_CHERIOT_CCALL;
       return ELF::R_RISCV_CHERI_CCALL;
     }

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1397,8 +1397,8 @@ def IsPureCapABI
 def NotPureCapABI
     : Predicate<"!RISCVABI::isCheriPureCapABI(Subtarget->getTargetABI())">;
 
-def FeatureVendorXCheriot1
-    : RISCVExtension<1, 0, "Implements Cheriot1 extension">;
+def FeatureVendorXCheriot
+    : RISCVExtension<1, 0, "Implements XCheriot extension">;
 
 def FeatureRelax
     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -599,6 +599,6 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
 // NB: FeatureCheri =>'s RVC (!FeatureCheriNoRVC)
 def CHERIOT : RISCVProcessorModel<"cheriot", NoSchedModel,
                                   [Feature32Bit, FeatureVendorXCheri,
-                                   FeatureVendorXCheriot1, FeatureCapMode,
+                                   FeatureVendorXCheriot, FeatureCapMode,
                                    FeatureStdExtC, FeatureStdExtE,
                                    FeatureStdExtM, FeatureUnalignedScalarMem]>;

llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

@@ -1077,7 +1077,7 @@ R"(All available -march extensions for RISC-V
     svpbmt               1.0
     svvptc               1.0
     xcheri               0.0
-    xcheriot1            1.0
+    xcheriot             1.0
     xcvalu               1.0
     xcvbi                1.0
     xcvbitmanip          1.0