Integrate more changes from big CHERI

clang/include/clang/Driver/Options.td

@@ -5111,14 +5111,6 @@ def mno_xcheri_rvc : Flag<["-"], "mno-xcheri-rvc">, Alias<mxcheri_norvc>;
 def mno_xcheri_norvc : Flag<["-"], "mno-xcheri-norvc">, Group<m_riscv_Features_Group>,
   HelpText<"Enable using compressed CHERI instructions">;
 def mxcheri_rvc : Flag<["-"], "mxcheri-rvc">, Alias<mno_xcheri_norvc>;
-// Temporary flags to enable/disable CHERI ISAv8 compatibility.
-// Flag name is a bit odd but this is required by handleTargetFeaturesGroup().
-def mxcheri_v9_semantics : Flag<["-"], "mxcheri-v9-semantics">, Group<m_riscv_Features_Group>,
-  HelpText<"Generate code that is no longer compatible with CHERI ISAv8">;
-def mno_xcheri_v9_semantics : Flag<["-"], "mno-xcheri-v9-semantics">, Group<m_riscv_Features_Group>,
-  HelpText<"Generate code that is compatible with CHERI ISAv8">;
-// Add an alias with a more sensible name for when the default is flipped.
-def mxcheri_v8_compat : Flag<["-"], "mxcheri-v8-compat">, Alias<mno_xcheri_v9_semantics>;
 
 def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_Group>,
   HelpText<"Allow memory accesses to be unaligned (AArch32/MIPSr6 only)">;

clang/lib/Basic/Targets/RISCV.cpp

@@ -317,11 +317,9 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
     // for the capability-mode JALR with immediate). Remove after the next
     // CHERI-LLVM "release".
     Builder.defineMacro("__riscv_xcheri_mode_dependent_jumps");
-    // Temporary defines to allow software to detect a new ISAv9 compiler.
-    if (HasCheriISAv9Semantics) {
-      Builder.defineMacro("__riscv_xcheri_tag_clear");
-      Builder.defineMacro("__riscv_xcheri_no_relocation");
-    }
+    // Defines to allow software to detect a ISAv9 compiler vs. an older v8 one.
+    Builder.defineMacro("__riscv_xcheri_tag_clear");
+    Builder.defineMacro("__riscv_xcheri_no_relocation");
   }
 
   if (ISAInfo->hasExtension("zve32x"))
@@ -463,8 +461,6 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
   if (ISAInfo->hasExtension("xcheri")) {
     HasCheri = true;
     CapSize = XLen * 2;
-    HasCheriISAv9Semantics =
-        llvm::is_contained(Features, "+xcheri-v9-semantics");
   }
   if (ABI.empty())
     ABI = ISAInfo->computeDefaultABI().str();

clang/lib/Basic/Targets/RISCV.h

@@ -73,7 +73,6 @@ class RISCVTargetInfo : public TargetInfo {
   std::unique_ptr<llvm::RISCVISAInfo> ISAInfo;
   int CapSize = -1;
   bool HasCheri = false;
-  bool HasCheriISAv9Semantics = false;
   bool IsABICHERIoT = false;
   bool IsABICHERIoTBareMetal = false;
   void setCapabilityABITypes() {

clang/test/CodeGen/cheri/cheri-hybrid-ptr-to-cap.c

@@ -8,6 +8,7 @@
 
 // Check the assembly output to see if we used PCC or DDC
 // RUN: %cheri_cc1 -o - -S %s | FileCheck %s --check-prefixes=ASM,ASM-MIPS
+// RUN: %riscv64_cheri_cc1 -o - -S %s
 // RUN: %riscv64_cheri_cc1 -o - -S %s | FileCheck %s --check-prefixes=ASM,ASM-RISCV
 
 void external_fn(void);
@@ -25,11 +26,11 @@ void *__capability global_fn_to_cap(void) {
   // ASM-MIPS:      cgetpcc $c1
   // ASM-MIPS-NEXT: ld $1, %got_disp(external_fn)($1)
   // ASM-MIPS-NEXT: cfromptr $c3, $c1, $1
-  // ASM-RISCV: cspecialr ca0, pcc
-  // ASM-RISCV: auipc a1, %got_pcrel_hi(external_fn)
-  // ASM-RISCV-NEXT:  ld a1, %pcrel_lo(.Lpcrel_hi0)(a1)
-  // ASM-RISCV-NEXT:  cfromptr ca0, ca0, a1
-  return (__cheri_tocap void *__capability) & external_fn;
+  // ASM-RISCV: cspecialr ca1, pcc
+  // ASM-RISCV: auipc a0, %got_pcrel_hi(external_fn)
+  // ASM-RISCV-NEXT:  ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
+  // ASM-RISCV-NEXT:  csetaddr ca1, ca1, a0
+  return (__cheri_tocap void *__capability)&external_fn;
 }
 
 // CHECK-LABEL: define {{[^@]+}}@global_data_to_cap
@@ -45,10 +46,11 @@ void *__capability global_data_to_cap(void) {
   // ASM-MIPS-NEXT: csetbounds $c3, $c1, 4
   // ASM-RISCV: auipc a0, %got_pcrel_hi(external_global)
   // ASM-RISCV-NEXT:  ld a0, %pcrel_lo(.Lpcrel_hi1)(a0)
-  // ASM-RISCV-NEXT:  cfromptr ca0, ddc, a0
+  // ASM-RISCV-NEXT:  cspecialr ca1, ddc
+  // ASM-RISCV-NEXT:  csetaddr ca1, ca1, a0
   // We do not set bounds on RISCV
   // ASM-RISCV-NOT: csetbounds
-  return (__cheri_tocap void *__capability) & external_global;
+  return (__cheri_tocap void *__capability)&external_global;
 }
 
 // CHECK-LABEL: define {{[^@]+}}@fn_ptr_to_cap
@@ -66,8 +68,8 @@ void *__capability fn_ptr_to_cap(void (*fn_ptr)(void)) {
   // ASM-LABEL: fn_ptr_to_cap:
   // ASM-MIPS:      cgetpcc $c1
   // ASM-MIPS-NEXT: cfromptr $c3, $c1, $1
-  // ASM-RISCV:      cspecialr ca0, pcc
-  // ASM-RISCV-NEXT: cfromptr ca0, ca0, a1
+  // ASM-RISCV:      cspecialr ca1, pcc
+  // ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
   return (__cheri_tocap void *__capability)fn_ptr;
 }
 
@@ -86,7 +88,8 @@ void *__capability fn_ptr_to_cap(void (*fn_ptr)(void)) {
 void *__capability fn_ptr_to_cap_not_smart_enough(void (*fn_ptr)(void)) {
   // ASM-LABEL: fn_ptr_to_cap_not_smart_enough:
   // ASM-MIPS:  cfromddc $c3, $1
-  // ASM-RISCV: cfromptr ca0, ddc, a0
+  // ASM-RISCV: cspecialr ca1, ddc
+  // ASM-RISCV-NEXT:  csetaddr ca1, ca1, a0
   // Note: In this case clang doesn't see that the result is actual a function
   // so it uses DDC:
   void *tmp = (void *)fn_ptr;
@@ -106,6 +109,7 @@ void *__capability data_ptr_to_cap(int *data_ptr) {
   // Note: For data pointers we derive from DDC:
   // ASM-LABEL: data_ptr_to_cap:
   // ASM-MIPS:  cfromddc $c3, $1
-  // ASM-RISCV: cfromptr ca0, ddc, a0
+  // ASM-RISCV: cspecialr ca1, ddc
+  // ASM-RISCV-NEXT:  csetaddr ca1, ca1, a0
   return (__cheri_tocap void *__capability)data_ptr;
 }

clang/test/Driver/riscv-default-features.c

@@ -1,44 +1,33 @@
 // RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
 // RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
 
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI
-// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mno-xcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI-NORVC
-// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mno-xcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-NORVC
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mxcheri-norvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI-NORVC
-// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mxcheri-norvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-NORVC
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV32-XCHERI,XCHERI
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV64-XCHERI,XCHERI
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mno-xcheri-rvc -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV32-XCHERI-NORVC,XCHERI
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mno-xcheri-rvc -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV64-XCHERI-NORVC,XCHERI
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mxcheri-norvc -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV32-XCHERI-NORVC,XCHERI
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mxcheri-norvc -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV64-XCHERI-NORVC,XCHERI
 // The -mxcheri-rvc flag to explicitly disable xcheri-norvc:
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mxcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI-EXPLICIT-RVC
-// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mxcheri-rvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-EXPLICIT-RVC
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mno-xcheri-norvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32-XCHERI-EXPLICIT-RVC
-// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mno-xcheri-norvc -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-EXPLICIT-RVC
-
-// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -mxcheri-v9-semantics -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-V9
-// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -mxcheri-v8-compat -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-V8
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mxcheri-rvc -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV32-XCHERI,XCHERI,XCHERI-RVC
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mxcheri-rvc -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV64-XCHERI,XCHERI,XCHERI-RVC
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixcheri -S -mno-xcheri-norvc -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV32-XCHERI,XCHERI,XCHERI-RVC
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -S -mno-xcheri-norvc -emit-llvm %s -o - | FileCheck %s --check-prefixes=RV64-XCHERI,XCHERI,XCHERI-RVC
 
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
 
-// RV32-XCHERI: "target-features"="+32bit,+relax,+xcheri
-// RV64-XCHERI: "target-features"="+64bit,+relax,+xcheri
+// RV32-XCHERI: "target-features"="+32bit,+relax,+xcheri,
+// RV64-XCHERI: "target-features"="+64bit,+relax,+xcheri,
 
 // RV32-XCHERI-RVC: "target-features"="+32bit,+relax,+xcheri
-// RV32-XCHERI-RVC: -save-restore
 // RV64-XCHERI-RVC: "target-features"="+64bit,+relax,+xcheri
-// RV64-XCHERI-RVC: -save-restore
 // RV32-XCHERI-NORVC: "target-features"="+32bit,+relax,+xcheri,+xcheri-norvc
 // RV64-XCHERI-NORVC: "target-features"="+64bit,+relax,+xcheri,+xcheri-norvc
 // RV32-XCHERI-EXPLICIT-RVC: "target-features"="+32bit,+relax,+xcheri
-// RV32-XCHERI-EXPLICIT-RVC-SAME -save-restore
-// RV32-XCHERI-EXPLICIT-RVC-SAME -xcheri-norvc
+// XCHERI-RVC-SAME: ,-xcheri-norvc,
 // RV64-XCHERI-EXPLICIT-RVC: "target-features"="+64bit,+relax,+xcheri
-// RV64-XCHERI-EXPLICIT-RVC-SAME -save-restore
-// RV64-XCHERI-EXPLICIT-RVC-SAME -xcheri-norvc
 
-// RV64-XCHERI-V8: "target-features"="+64bit,+relax,+xcheri
-// RV64-XCHERI-V8-SAME: -xcheri-v9-semantics
-// RV64-XCHERI-V9: "target-features"="+64bit,+relax,+xcheri
-// RV64-XCHERI-V9-SAME: +xcheri-v9-semantics
+// XCHERI-NOT: xcheri,
 
 // Dummy function
 int foo(void){

clang/test/Preprocessor/cheri-riscv-feature-flags.c

@@ -1,11 +1,6 @@
 // RUN: %riscv64_cheri_cc1 -E -dM -ffreestanding < /dev/null \
-// RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK64 --implicit-check-not=cheri --implicit-check-not=CHERI
-// RUN: %riscv32_cheri_cc1 -E -dM -ffreestanding < /dev/null \
-// RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK32 --implicit-check-not=cheri --implicit-check-not=CHERI
-/// Check for the new flags for removed ISAv8 compatibility:
-// RUN: %riscv64_cheri_cc1 -E -dM -ffreestanding -target-feature +xcheri-v9-semantics < /dev/null \
 // RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK64,CHECK-V9ISA --implicit-check-not=cheri --implicit-check-not=CHERI
-// RUN: %riscv32_cheri_cc1 -E -dM -ffreestanding -target-feature +xcheri-v9-semantics < /dev/null \
+// RUN: %riscv32_cheri_cc1 -E -dM -ffreestanding < /dev/null \
 // RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK32,CHECK-V9ISA --implicit-check-not=cheri --implicit-check-not=CHERI
 
 // CHECK32: #define __CHERI_ADDRESS_BITS__ 32

lld/ELF/Arch/Cheri.cpp

@@ -14,10 +14,6 @@ using namespace llvm;
 using namespace llvm::object;
 using namespace llvm::ELF;
 
-// Change these to #define for extremely verbose debug output
-#undef DEBUG_CAP_RELOCS
-#undef DEBUG_CAP_TABLE
-
 namespace lld {
 namespace elf {
 
@@ -355,13 +351,6 @@ void CheriCapRelocsSection::addCapReloc(CheriCapRelocLocation loc,
     return;  // Maybe happens with vtables?
   }
   if (targetNeedsDynReloc) {
-#ifdef DEBUG_CAP_RELOCS
-    message("Adding dyn reloc at " + toString(this) + "+0x" +
-            utohexstr(CurrentEntryOffset) + " against " +
-            Target.verboseToString());
-    message("Symbol preemptible:" + Twine(Target.Sym->IsPreemptible));
-#endif
-
     bool relativeToLoadAddress = false;
     // The addend is not used as the offset into the capability here, as we
     // have the offset field in the __cap_relocs for that. The Addend
@@ -468,12 +457,6 @@ static uint64_t getTargetSize(Ctx &ctx, const CheriCapRelocLocation &location,
       // past the section
       if (offsetInOS <= os->size) {
         targetSize = os->size - offsetInOS;
-#ifdef DEBUG_CAP_RELOCS
-        if (ctx.arg.verboseCapRelocs)
-          errs() << " OS OFFSET 0x" << utohexstr(OS->Addr) << "SYM OFFSET 0x"
-                 << utohexstr(OffsetInOS) << " SECLEN 0x" << utohexstr(OS->Size)
-                 << " -> target size 0x" << utohexstr(TargetSize) << "\n";
-#endif
         UnknownSectionSize = false;
       }
     }
@@ -715,17 +698,6 @@ void CheriCapTableSection::addEntry(Symbol &sym, RelExpr expr,
     // TODO: should we emit two relocations instead?
     if (!idx.usedInCallExpr) it.first->second.usedInCallExpr = false;
   }
-#if defined(DEBUG_CAP_TABLE)
-  std::string DbgContext;
-  if (ctx.arg.CapTableScope == CapTableScopePolicy::File) {
-    DbgContext = " for file '" + toString(IS->File) + "'";
-  } else if (ctx.arg.CapTableScope == CapTableScopePolicy::Function) {
-    DbgContext =
-        " for function '" + toString(*findMatchingFunction(IS, Offset)) + "'";
-  }
-  llvm::errs() << "Added symbol " << toString(Sym) << " to .captable"
-               << DbgContext << ". Total count " << Entries.size() << "\n";
-#endif
 }
 
 void CheriCapTableSection::addDynTlsEntry(Symbol &sym) {
@@ -755,11 +727,6 @@ uint32_t CheriCapTableSection::getIndex(const Symbol &sym,
   // start of the current captable subset (or the global table in the default
   // case). When using per-function tables the first index in every function
   // will always be zero.
-#if defined(DEBUG_CAP_TABLE)
-  message("captable index for " + toString(Sym) + " is " +
-          Twine(*it->second.Index) + " - " + Twine(Entries.FirstIndex) + ": " +
-          Twine(*it->second.Index - Entries.FirstIndex));
-#endif
   return *it->second.index - entries.firstIndex;
 }
 

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -1356,20 +1356,6 @@ def RV64           : HwMode<"+64bit", [IsRV64]>;
 def IsRVE : Predicate<"Subtarget->isRVE()">,
             AssemblerPredicate<(all_of FeatureStdExtE)>;
 
-// TODO: Once all supported CheriBSD branches are ready for the new semantics
-// this feature should be enabled automatically.
-def FeatureCheriISAV9Semantics
-    : SubtargetFeature<"xcheri-v9-semantics", "HasCheriISAv9Semantics", "true",
-                       "CHERI ISAv9 semantics (tag-clearing, no relocation)">;
-def HasCheriISAv9
-    : Predicate<"Subtarget->hasCheriISAv9Semantics()">,
-                AssemblerPredicate<(all_of FeatureCheriISAV9Semantics),
-                "CHERI ISAv9 semantics (tag-clearing, no relocation)">;
-def NotCheriISAv9
-    : Predicate<"!Subtarget->hasCheriISAv9Semantics()">,
-                AssemblerPredicate<(all_of (not FeatureCheriISAV9Semantics)),
-                "CHERI ISAv8 semantics (trapping, DDC/PCC relocation)">;
-
 def FeatureVendorXCheri : RISCVExtension<0, 0, "Implements CHERI extension">;
 
 def HasCheri : Predicate<"Subtarget->hasVendorXCheri()">,

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -672,8 +672,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::GlobalTLSAddress, CLenVT, Custom);
     setOperationAction(ISD::ADDRSPACECAST, CLenVT, Custom);
     setOperationAction(ISD::ADDRSPACECAST, XLenVT, Custom);
-    if (Subtarget.hasCheriISAv9Semantics() &&
-        !RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())) {
+    if (!RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())) {
       setOperationAction(ISD::PTRTOINT, XLenVT, Custom);
       setOperationAction(ISD::INTTOPTR, CLenVT, Custom);
     }
@@ -6909,8 +6908,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::INTTOPTR: {
     SDValue Op0 = Op.getOperand(0);
     if (Op.getValueType().isFatPointer()) {
-      assert(Subtarget.hasCheriISAv9Semantics() &&
-             !RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()));
+      assert(!RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()));
       if (isNullConstant(Op0)) {
         // Do not custom lower (inttoptr 0) here as that is the canonical
         // representation of capability NULL, and expanding it here disables
@@ -6936,8 +6934,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::PTRTOINT: {
     SDValue Op0 = Op.getOperand(0);
     if (Op0.getValueType().isFatPointer()) {
-      assert(Subtarget.hasCheriISAv9Semantics() &&
-             !RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()));
+      assert(!RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()));
       // In purecap ptrtoint is lowered to an address read using a tablegen
       // pattern, but for hybrid mode we need to emit the expansion here as
       // CToPtr is no longer part of ISAv9.
@@ -10064,22 +10061,15 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                        Index);
   }
   case Intrinsic::cheri_cap_from_pointer:
-    // Expand CFromPtr if the dedicated instruction has been removed.
-    if (Subtarget.hasCheriISAv9Semantics()) {
-      return emitCFromPtrReplacement(DAG, DL, Op.getOperand(1),
-                                     Op.getOperand(2), Op.getValueType(),
-                                     XLenVT);
-    }
-    break;
+    // Expand CFromPtr since the dedicated instruction has been removed.
+    return emitCFromPtrReplacement(DAG, DL, Op.getOperand(1), Op.getOperand(2),
+                                   Op.getValueType(), XLenVT);
   case Intrinsic::cheri_cap_to_pointer:
-    // Expand CToPtr if the dedicated instruction has been removed.
-    if (Subtarget.hasCheriISAv9Semantics()) {
-      // NB: DDC/PCC relocation has been removed, so we no longer subtract the
-      // base of the authorizing capability. This is consistent with the
-      // behaviour of Morello's CVT instruction when CCTLR.DDCBO is off.
-      return emitCToPtrReplacement(DAG, DL, Op->getOperand(2), XLenVT);
-    }
-    break;
+    // Expand CToPtr since the dedicated instruction has been removed.
+    // NB: DDC/PCC relocation has been removed, so we no longer subtract the
+    // base of the authorizing capability. This is consistent with the
+    // behaviour of Morello's CVT instruction when CCTLR.DDCBO is off.
+    return emitCToPtrReplacement(DAG, DL, Op->getOperand(2), XLenVT);
   case Intrinsic::thread_pointer: {
     MCPhysReg PhysReg = RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())
         ? RISCV::C4 : RISCV::X4;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -1814,39 +1814,7 @@ bool RISCVInstrInfo::isSetBoundsInstr(const MachineInstr &I,
 }
 
 bool RISCVInstrInfo::isGuaranteedNotToTrap(const llvm::MachineInstr &MI) const {
-  const RISCVSubtarget &ST = MI.getMF()->getSubtarget<RISCVSubtarget>();
-  // TODO: This function can be removed once ISAv8 semantics are no longer
-  // supported and the tablegen definitions have been updated to remove the
-  // mayTrap/@traps_if_sealed flags.
-  if (ST.hasCheriISAv9Semantics()) {
-    // All these instructions were changed to non-trapping.
-    switch (MI.getOpcode()) {
-    case RISCV::CAndPerm:
-    case RISCV::CBuildCap:
-    case RISCV::CCopyType:
-    case RISCV::CCSeal:
-    case RISCV::CFromPtr:
-    case RISCV::CIncOffset:
-    case RISCV::CIncOffsetImm:
-    case RISCV::CSeal:
-    case RISCV::CSealEntry:
-    case RISCV::CSetAddr:
-    case RISCV::CSetBounds:
-    case RISCV::CSetBoundsExact:
-    case RISCV::CSetBoundsImm:
-    case RISCV::CSetFlags:
-    case RISCV::CSetHigh:
-    case RISCV::CSetOffset:
-    case RISCV::CToPtr:
-    case RISCV::CUnseal:
-      return true;
-    default:
-      llvm_unreachable("Unexpected instruction in isGuaranteedNotToTrap");
-      return false;
-    }
-  }
-  if (isGuaranteedValidSetBounds(MI))
-    return true;
+  llvm_unreachable("Should not be called for any CHERI-RISC-V instructions");
   return false;
 }