CHERIoT-Platform · resistor · Aug 16, 2025 · Aug 15, 2025
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
@@ -379,7 +379,7 @@ bool RISCVTargetInfo::initFeatureMap(
 
   if (getTriple().getSubArch() == llvm::Triple::RISCV32SubArch_cheriot_v1) {
     Features["xcheri"] = true;
-    Features["cap-mode"] = true;
+    Features["xcheripurecap"] = true;
     Features["c"] = true;
     Features["e"] = true;
     Features["m"] = true;

diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -220,7 +220,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
             << "pure capability ABI requires xcheri extension to be specified";
         return;
       }
-      Features.push_back("+cap-mode");
+      Features.push_back("+xcheripurecap");
     }
   }
 
@@ -232,7 +232,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
           << "pure capability ABI requires xcheri extension to be specified";
         return;
       }
-      Features.push_back("+cap-mode");
+      Features.push_back("+xcheripurecap");
     }
   }
 
@@ -244,7 +244,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
           << "pure capability ABI requires xcheri extension to be specified";
         return;
       }
-      Features.push_back("+cap-mode");
+      Features.push_back("+xcheripurecap");
     }
   }
 
@@ -256,7 +256,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
           << "pure capability ABI requires xcheri extension to be specified";
         return;
       }
-      Features.push_back("+cap-mode");
+      Features.push_back("+xcheripurecap");
     }
   }
 

diff --git a/clang/test/CodeGen/cheri/cheriot-struct-ret.c b/clang/test/CodeGen/cheri/cheriot-struct-ret.c
@@ -810,6 +810,6 @@ __attribute__((cheri_compartment("example"))) void CheckOnePtr () {
 }
 
 
-// CHECK: attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
-// CHECK: attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
-// CHECK: attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
+// CHECK: attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }
+// CHECK: attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }
+// CHECK: attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }
diff --git a/clang/test/CodeGen/cheri/riscv/cheriot-static-sealed-value-attr.c b/clang/test/CodeGen/cheri/riscv/cheriot-static-sealed-value-attr.c
@@ -42,6 +42,6 @@ void func() {
 // CHECK: declare void @doSomething2(ptr addrspace(200) noundef) local_unnamed_addr addrspace(200) #2
 
 // CHECK: attributes #0 = { "cheriot_sealed_value" }
-// CHECK: attributes #1 = { minsize nounwind optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
-// CHECK: attributes #2 = { minsize optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" }
+// CHECK: attributes #1 = { minsize nounwind optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }
+// CHECK: attributes #2 = { minsize optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" }
 // CHECK: attributes #3 = { minsize nounwind optsize }
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -152,6 +152,7 @@
 // CHECK-NEXT:     svvptc               1.0       'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
 // CHECK-NEXT:     xcheri               0.0       'XCheri' (Implements CHERI extension)
 // CHECK-NEXT:     xcheriot             1.0       'XCheriot' (Implements XCheriot extension)
+// CHECK-NEXT:     xcheripurecap        0.0       'XCheriPureCap' (Implements CHERI pure capability mode)
 // CHECK-NEXT:     xcvalu               1.0       'XCValu' (CORE-V ALU Operations)
 // CHECK-NEXT:     xcvbi                1.0       'XCVbi' (CORE-V Immediate Branching)
 // CHECK-NEXT:     xcvbitmanip          1.0       'XCVbitmanip' (CORE-V Bit Manipulation)

diff --git a/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s b/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s
@@ -1,10 +1,10 @@
 # REQUIRES: riscv
-# RUN: llvm-mc -triple=riscv32cheriot-unknown-cheriotrtos -mcpu=cheriot -mattr=+c,+xcheri,+xcheriot -filetype=obj %s -o %t.o
+# RUN: llvm-mc -triple=riscv32cheriot-unknown-cheriotrtos -mcpu=cheriot -mattr=+c,+xcheri,+xcheripurecap,+xcheriot -filetype=obj %s -o %t.o
 # RUN: ld.lld %t.o -o %t.exe
 # RUN: llvm-objdump -d %t.exe | FileCheck %s
 
 	.attribute	4, 16
-	.attribute	5, "rv32e2p0_m2p0_c2p0_zmmul1p0_xcheri0p0_xcheriot1p0"
+	.attribute	5, "rv32e2p0_m2p0_c2p0_zmmul1p0_xcheri0p0_xcheriot1p0_xcheripurecap1p0"
 	.section	.text,"ax",@progbits
 	.globl	_start
 	.p2align	1
@@ -43,8 +43,8 @@ _start:                              # @_Z5entryv
 near:
 	.word 1
 
-# CHECK:      00012010 <near>:
-# CHECK-NEXT: 12010: 01 00 00 00 00 00 00 00
+# CHECK:      00012020 <near>:
+# CHECK-NEXT: 12020: 01 00 00 00 00 00 00 00
 
 	.type	mid,@object
 	.p2align	12, 0x0

diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp
@@ -383,7 +383,7 @@ Expected<SubtargetFeatures> ELFObjectFileBase::getRISCVFeatures() const {
 
   if (PlatformFlags & ELF::EF_RISCV_CAP_MODE) {
     Features.AddFeature("xcheri");
-    Features.AddFeature("cap-mode");
+    Features.AddFeature("xcheripurecap");
   }
 
   RISCVAttributeParser Attributes;

diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3427,7 +3427,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
                    "option requires 'xcheri' extension");
 
     getTargetStreamer().emitDirectiveOptionCapMode();
-    setFeatureBits(RISCV::FeatureCapMode, "cap-mode");
+    setFeatureBits(RISCV::FeatureVendorXCheriPureCap, "xcheripurecap");
     return false;
   }
 
@@ -3440,7 +3440,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
                    "option requires 'xcheri' extension");
 
     getTargetStreamer().emitDirectiveOptionNoCapMode();
-    clearFeatureBits(RISCV::FeatureCapMode, "cap-mode");
+    clearFeatureBits(RISCV::FeatureVendorXCheriPureCap, "xcheripurecap");
     return false;
   }
 

diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -668,14 +668,14 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
 
   uint32_t Insn = support::endian::read32le(Bytes.data());
 
-    TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureCapMode) &&
-                      !STI.hasFeature(RISCV::Feature64Bit),
-                  DecoderTableRISCV32CapModeOnly_32,
-                  "RISCV32CapModeOnly_32 table");
-    TRY_TO_DECODE(!STI.hasFeature(RISCV::Feature64Bit),
-                  DecoderTableRISCV32Only_32, "RISCV32Only_32 table");
-    TRY_TO_DECODE_FEATURE(RISCV::FeatureCapMode, DecoderTableCapModeOnly_32,
-                          "CapModeOnly_32 table");
+  TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureVendorXCheriPureCap) &&
+                    !STI.hasFeature(RISCV::Feature64Bit),
+                DecoderTableRISCV32CapModeOnly_32,
+                "RISCV32CapModeOnly_32 table");
+  TRY_TO_DECODE(!STI.hasFeature(RISCV::Feature64Bit),
+                DecoderTableRISCV32Only_32, "RISCV32Only_32 table");
+  TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCheriPureCap,
+                        DecoderTableCapModeOnly_32, "CapModeOnly_32 table");
   TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
                     !STI.hasFeature(RISCV::Feature64Bit),
                 DecoderTableRV32Zdinx32,
@@ -794,11 +794,11 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
   Size = 2;
 
   uint32_t Insn = support::endian::read16le(Bytes.data());
-  TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit) &&
-                               STI.hasFeature(RISCV::FeatureCapMode),
-                           DecoderTableRISCV32CapModeOnly_16,
-                           "RISCV32CapModeOnly_16");
-  TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureCapMode),
+  TRY_TO_DECODE_AND_ADD_SP(
+      !STI.hasFeature(RISCV::Feature64Bit) &&
+          STI.hasFeature(RISCV::FeatureVendorXCheriPureCap),
+      DecoderTableRISCV32CapModeOnly_16, "RISCV32CapModeOnly_16");
+  TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXCheriPureCap),
                            DecoderTableCapModeOnly_16, "CapModeOnly_16 table");
   TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
                            DecoderTableRISCV32Only_16,

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -368,7 +368,7 @@ std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,
 // Given a compressed control flow instruction this function returns
 // the expanded instruction.
 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
-  bool IsCapMode = STI.getFeatureBits()[RISCV::FeatureCapMode];
+  bool IsCapMode = STI.getFeatureBits()[RISCV::FeatureVendorXCheriPureCap];
 
   switch (Op) {
   default:

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -148,8 +148,8 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
   if (FeatureBits[RISCV::FeatureVendorXCheriot]) {
     if (!FeatureBits[RISCV::FeatureVendorXCheri])
       report_fatal_error("XCheriot extension requires XCheri extension");
-    if (!FeatureBits[RISCV::FeatureCapMode])
-      report_fatal_error("XCheriot extension requires CapMode");
+    if (!FeatureBits[RISCV::FeatureVendorXCheriPureCap])
+      report_fatal_error("XCheriot extension requires XCheriPureCap");
   }
 }
 

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -62,7 +62,7 @@ void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) {
   HasRVC = STI.hasFeature(RISCV::FeatureStdExtC) ||
            STI.hasFeature(RISCV::FeatureStdExtZca);
   HasTSO = STI.hasFeature(RISCV::FeatureStdExtZtso);
-  IsCapMode = STI.hasFeature(RISCV::FeatureCapMode);
+  IsCapMode = STI.hasFeature(RISCV::FeatureVendorXCheriPureCap);
 }
 
 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1368,15 +1368,15 @@ def HasCheriRVC : Predicate<"Subtarget->enableCheriRVCInstrs()">,
                   AssemblerPredicate<(all_of (not FeatureCheriNoRVC)),
                                      "CHERI RVC Instructions">;
 
-def FeatureCapMode
-    : SubtargetFeature<"cap-mode", "IsCapMode", "true",
-                       "Capability mode">;
-def IsCapMode  : Predicate<"Subtarget->isCapMode()">,
-                           AssemblerPredicate<(all_of FeatureCapMode),
-                           "Capability Mode">;
-def NotCapMode : Predicate<"!Subtarget->isCapMode()">,
-                           AssemblerPredicate<(all_of (not FeatureCapMode)),
-                           "Not Capability Mode">;
+def FeatureVendorXCheriPureCap
+    : RISCVExtension<
+          0, 0, "Implements CHERI pure capability mode", [FeatureVendorXCheri]>;
+def IsCapMode : Predicate<"Subtarget->hasVendorXCheriPureCap()">,
+                AssemblerPredicate<(all_of FeatureVendorXCheriPureCap),
+                                   "Capability Mode">;
+def NotCapMode : Predicate<"!Subtarget->hasVendorXCheriPureCap()">,
+                 AssemblerPredicate<(all_of(not FeatureVendorXCheriPureCap)),
+                                    "Not Capability Mode">;
 
 def IsPureCapABI
     : Predicate<"RISCVABI::isCheriPureCapABI(Subtarget->getTargetABI())">;

diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -597,8 +597,9 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
                                           FeatureStdExtZcmp]>;
 
 // NB: FeatureCheri =>'s RVC (!FeatureCheriNoRVC)
-def CHERIOT : RISCVProcessorModel<"cheriot", NoSchedModel,
-                                  [Feature32Bit, FeatureVendorXCheri,
-                                   FeatureVendorXCheriot, FeatureCapMode,
-                                   FeatureStdExtC, FeatureStdExtE,
-                                   FeatureStdExtM, FeatureUnalignedScalarMem]>;
+def CHERIOT
+    : RISCVProcessorModel<"cheriot", NoSchedModel,
+                          [Feature32Bit, FeatureVendorXCheri,
+                           FeatureVendorXCheriot, FeatureVendorXCheriPureCap,
+                           FeatureStdExtC, FeatureStdExtE, FeatureStdExtM,
+                           FeatureUnalignedScalarMem]>;
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll
@@ -2,8 +2,8 @@
 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/atomic-rmw-cap-ptr-arg.ll
 ; Check that we can generate sensible code for atomic operations using capability pointers on capabilities
 ; See https://github.com/CTSRD-CHERI/llvm-project/issues/470
-; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes
-; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes
+; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes
+; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes
 ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-ATOMICS --allow-unused-prefixes
 ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=-a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-LIBCALLS --allow-unused-prefixes
 

diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll
@@ -2,8 +2,8 @@
 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/atomic-rmw-cap-ptr.ll
 ; Check that we can generate sensible code for atomic operations using capability pointers
 ; https://github.com/CTSRD-CHERI/llvm-project/issues/470
-; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes
-; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes
+; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes
+; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes
 ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-ATOMICS --allow-unused-prefixes
 ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=-a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-LIBCALLS --allow-unused-prefixes
 

diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll
@@ -2,7 +2,7 @@
 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/bounded-allocas-lifetimes.ll
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; CHERI-GENERIC-UTC: mir
-; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - --stop-after=finalize-isel | FileCheck %s
+; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - --stop-after=finalize-isel | FileCheck %s
 
 ; Check that lifetime markers don't get lost due to CheriBoundAllocas, as we'd
 ; risk StackSlotColoring reusing the slot.

diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll
@@ -3,8 +3,8 @@
 ;; Check that we can correctly generate code for llvm.cheri.cap.from.pointer()
 ;; This previously asserted on RISC-V due to a broken ISel pattern.
 ;; We pipe this input through instcombine first to ensure SelectionDAG sees canonical IR.
-; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -passes=instcombine -S < %s | FileCheck %s --check-prefix=CHECK-IR
-; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -passes=instcombine -S < %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f | FileCheck %s --check-prefix=PURECAP
+; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -passes=instcombine -S < %s | FileCheck %s --check-prefix=CHECK-IR
+; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -passes=instcombine -S < %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f | FileCheck %s --check-prefix=PURECAP
 ; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -passes=instcombine -S < %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f | FileCheck %s --check-prefix=HYBRID
 
 define internal ptr addrspace(200) @test(ptr addrspace(200) %ptr, ptr addrspace(200) %cap, i32 %offset) addrspace(200) nounwind {

diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-csub.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-csub.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2
 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/cheri-csub.ll
 ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f %s -o - | FileCheck %s --check-prefix=HYBRID
-; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - | FileCheck %s --check-prefix=PURECAP
+; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - | FileCheck %s --check-prefix=PURECAP
 
 define i32 @subp(i8 addrspace(200)* readnone %a, i8 addrspace(200)* readnone %b) nounwind {
 ; HYBRID-LABEL: subp:

diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll
@@ -3,8 +3,8 @@
 ; This used to create a broken function.
 ; FIXME: the getoffset+add sequence should be folded to an increment
 ; REQUIRES: mips-registered-target
-; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -S -passes=instcombine %s -o - | FileCheck %s
-; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -S '-passes=default<O3>' %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O3 -o - | FileCheck %s --check-prefix ASM
+; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -S -passes=instcombine %s -o - | FileCheck %s
+; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -S '-passes=default<O3>' %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O3 -o - | FileCheck %s --check-prefix ASM
 target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200"
 
 @d = common addrspace(200) global i32 0, align 4