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Merged
arichardson merged 5 commits into from
Nov 7, 2025
Merged

Rvy093 shadd #293

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923782e
RVY: Implement SHxADD mode-dependent instructions
buxtonpaul Mar 27, 2025
a3523c9
RVY: Implement SHxADD.UW mode-dependent instructions
buxtonpaul Mar 28, 2025
99ab770
RVY: Implement the add.uw mode-dependent instruction
buxtonpaul Mar 28, 2025
cc01941
RVY: Add a zish4add extension configuration option.
buxtonpaul Aug 18, 2025
e5b29dc
RVY: Add the 0.9.3 sh4add(.uw) instructions
arichardson Oct 31, 2025
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4 changes: 4 additions & 0 deletions target/riscv/cpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1119,6 +1119,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),

#if defined(TARGET_CHERI_RISCV_STD_093)
/* zish4add is part of the cheri spec, so we enable it by default */
DEFINE_PROP_BOOL("zish4add", RISCVCPU, cfg.ext_zish4add, true),
#endif
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),

/* These are experimental so mark with 'x-' */
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3 changes: 3 additions & 0 deletions target/riscv/cpu.h
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Expand Up @@ -470,6 +470,9 @@ struct RISCVCPU {
uint8_t _compat_cheri_levels; /* To keep existing scripts working */
uint8_t lvbits; /* Only 0 and 1 (Zylevels1) are currently supported. */
bool cheri_pte;
#endif
#if defined(TARGET_CHERI_RISCV_STD_093)
bool ext_zish4add;
#endif
char *priv_spec;
char *user_spec;
Expand Down
6 changes: 5 additions & 1 deletion target/riscv/insn32-cheri-std.decode
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Expand Up @@ -98,4 +98,8 @@ sc ....... ..... ..... 100 ..... 0100011 @s ?pred_cre
# Atomic instructions
amoswap_c 00001 . . ..... ..... 100 ..... 0101111 @atom_st ?pred_cre
lr_c 00010 . . 00000 ..... 100 ..... 0101111 @atom_ld ?pred_cre
sc_c 00011 . . ..... ..... 100 ..... 0101111 @atom_st ?pred_cre
sc_c 00011 . . ..... ..... 100 ..... 0101111 @atom_st ?pred_cre

# Pre-0.9.6 mode-dependent sh4add instructions (sh4addy starting in 0.9.6)
sh4add 0010000 .......... 111 ..... 0110011 @r
sh4add_uw 0010000 .......... 111 ..... 0111011 @r
73 changes: 72 additions & 1 deletion target/riscv/insn_trans/trans_rvb.c.inc
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Expand Up @@ -42,6 +42,13 @@
} \
} while (0)

#define REQUIRE_ZISH4ADD(ctx) \
do { \
if (!RISCV_CPU(ctx->cs)->cfg.ext_zish4add) { \
return false; \
} \
} while (0)

static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
Expand Down Expand Up @@ -353,13 +360,38 @@ GEN_SHADD(1)
GEN_SHADD(2)
GEN_SHADD(3)

/* For RISC-V standard versions post 0.9.6 we allocate new encodings instead. */
#ifdef TARGET_CHERI_RISCV_STD_093
#define GEN_TRANS_SHADD(SHAMT) \
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
{ \
REQUIRE_ZBA(ctx); \
if (SHAMT == 4) { \
REQUIRE_ZISH4ADD(ctx); \
REQUIRE_64BIT(ctx); \
} \
if (ctx->capmode) { \
TCGv offset = tcg_temp_new(); \
gen_get_gpr(ctx, offset, a->rs1); \
tcg_gen_shli_tl(offset, offset, SHAMT); \
gen_helper_cincoffset(cpu_env, tcg_constant_i32(a->rd), \
tcg_constant_i32(a->rs2), offset); \
tcg_temp_free(offset); \
return true; \
} \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \
}

GEN_SHADD(4)
GEN_TRANS_SHADD(4)
#else
#define GEN_TRANS_SHADD(SHAMT) \
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
{ \
REQUIRE_ZBA(ctx); \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \
}

#endif
GEN_TRANS_SHADD(1)
GEN_TRANS_SHADD(2)
GEN_TRANS_SHADD(3)
Expand Down Expand Up @@ -441,6 +473,33 @@ GEN_SHADD_UW(1)
GEN_SHADD_UW(2)
GEN_SHADD_UW(3)

/* For RISC-V standard versions post 0.9.6 we allocate new encodings instead. */
#ifdef TARGET_CHERI_RISCV_STD_093
#define GEN_TRANS_SHADD_UW(SHAMT) \
static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
arg_sh##SHAMT##add_uw *a) \
{ \
REQUIRE_ZBA(ctx); \
REQUIRE_64BIT(ctx); \
if (SHAMT == 4) { \
REQUIRE_ZISH4ADD(ctx); \
} \
if (ctx->capmode) { \
TCGv offset = tcg_temp_new(); \
gen_get_gpr(ctx, offset, a->rs1); \
tcg_gen_ext32u_tl(offset, offset); \
tcg_gen_shli_tl(offset, offset, SHAMT); \
gen_helper_cincoffset(cpu_env, tcg_constant_i32(a->rd), \
tcg_constant_i32(a->rs2), offset); \
tcg_temp_free(offset); \
return true; \
} \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \
}

GEN_SHADD_UW(4)
GEN_TRANS_SHADD_UW(4)
#else
#define GEN_TRANS_SHADD_UW(SHAMT) \
static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
arg_sh##SHAMT##add_uw *a) \
Expand All @@ -450,6 +509,7 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \
}

#endif
GEN_TRANS_SHADD_UW(1)
GEN_TRANS_SHADD_UW(2)
GEN_TRANS_SHADD_UW(3)
Expand All @@ -466,6 +526,17 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBA(ctx);
#ifdef TARGET_CHERI_RISCV_STD_093
if (ctx->capmode) {
TCGv t = tcg_temp_new();
gen_get_gpr(ctx, t, a->rs1);
tcg_gen_ext32u_tl(t, t);
gen_helper_cincoffset(cpu_env, tcg_constant_i32(a->rd),
tcg_constant_i32(a->rs2), t);
tcg_temp_free(t);
return true;
}
#endif
return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
}

Expand Down
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