Add the Hobgoblin platform

configs/devices/riscv32-softmmu/default.mak

@@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=y
 CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
 CONFIG_OPENTITAN=y
+CONFIG_HOBGOBLIN=y

configs/devices/riscv64-softmmu/default.mak

@@ -14,3 +14,4 @@ CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
 CONFIG_MICROCHIP_PFSOC=y
 CONFIG_SHAKTI_C=y
+CONFIG_HOBGOBLIN=y

hw/char/xilinx_uartlite.c

@@ -48,6 +48,7 @@
 #define STATUS_OVERRUN    0x20
 #define STATUS_FRAME      0x40
 #define STATUS_PARITY     0x80
+#define STATUS_ERRORS     (STATUS_OVERRUN | STATUS_FRAME | STATUS_PARITY)
 
 #define CONTROL_RST_TX    0x01
 #define CONTROL_RST_RX    0x02
@@ -70,23 +71,20 @@ struct XilinxUARTLite {
     uint32_t regs[R_MAX];
 };
 
-static void uart_update_irq(XilinxUARTLite *s)
+static void uart_raise_irq(XilinxUARTLite *s)
 {
-    unsigned int irq;
-
-    if (s->rx_fifo_len)
-        s->regs[R_STATUS] |= STATUS_IE;
-
-    irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
-    qemu_set_irq(s->irq, irq);
+    if (s->regs[R_CTRL] & CONTROL_IE) {
+        qemu_irq_pulse(s->irq);
+    }
 }
 
 static void uart_update_status(XilinxUARTLite *s)
 {
     uint32_t r;
 
     r = s->regs[R_STATUS];
-    r &= ~7;
+    r &= STATUS_ERRORS;
+    r |= s->regs[R_CTRL] & STATUS_IE;
     r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */
     r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
     r |= (!!s->rx_fifo_len);
@@ -110,14 +108,23 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
             if (s->rx_fifo_len)
                 s->rx_fifo_len--;
+            else
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: read from empty FIFO\n",
+                              __func__);
             uart_update_status(s);
-            uart_update_irq(s);
             qemu_chr_fe_accept_input(&s->chr);
             break;
 
+        case R_CTRL:
+        case R_TX:
+            break;
+
+        case R_STATUS:
+            r = s->regs[addr];
+            s->regs[R_STATUS] &= ~STATUS_ERRORS;
+            break;
+
         default:
-            if (addr < ARRAY_SIZE(s->regs))
-                r = s->regs[addr];
             DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
             break;
     }
@@ -154,18 +161,17 @@ uart_write(void *opaque, hwaddr addr,
             qemu_chr_fe_write_all(&s->chr, &ch, 1);
             s->regs[addr] = value;
 
-            /* hax.  */
-            s->regs[R_STATUS] |= STATUS_IE;
+            uart_raise_irq(s);
+            break;
+
+        case R_RX:
             break;
 
         default:
             DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
-            if (addr < ARRAY_SIZE(s->regs))
-                s->regs[addr] = value;
             break;
     }
     uart_update_status(s);
-    uart_update_irq(s);
 }
 
 static const MemoryRegionOps uart_ops = {
@@ -190,6 +196,7 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
     /* Got a byte.  */
     if (s->rx_fifo_len >= 8) {
         printf("WARNING: UART dropped char.\n");
+        s->regs[R_STATUS] |= STATUS_OVERRUN;
         return;
     }
     s->rx_fifo[s->rx_fifo_pos] = *buf;
@@ -198,7 +205,8 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
     s->rx_fifo_len++;
 
     uart_update_status(s);
-    uart_update_irq(s);
+    if (s->rx_fifo_len == 1)
+        uart_raise_irq(s);
 }
 
 static int uart_can_rx(void *opaque)

hw/dma/xilinx_axidma.c

@@ -55,7 +55,9 @@ DECLARE_INSTANCE_CHECKER(XilinxAXIDMAStreamSink, XILINX_AXI_DMA_CONTROL_STREAM,
 #define R_DMACR             (0x00 / 4)
 #define R_DMASR             (0x04 / 4)
 #define R_CURDESC           (0x08 / 4)
+#define R_CURDESC_MSB       (0x0c / 4)
 #define R_TAILDESC          (0x10 / 4)
+#define R_TAILDESC_MSB      (0x14 / 4)
 #define R_MAX               (0x30 / 4)
 
 #define CONTROL_PAYLOAD_WORDS 5
@@ -121,6 +123,12 @@ struct XilinxAXIDMAStreamSink {
     struct XilinxAXIDMA *dma;
 };
 
+enum {
+    XILINX_AXIDMA_FLAG_64BIT_BIT,
+};
+
+#define XILINX_AXIDMA_FLAG_64BIT (1 << XILINX_AXIDMA_FLAG_64BIT_BIT)
+
 struct XilinxAXIDMA {
     SysBusDevice busdev;
     MemoryRegion iomem;
@@ -132,6 +140,7 @@ struct XilinxAXIDMA {
     StreamSink *tx_control_dev;
     XilinxAXIDMAStreamSink rx_data_dev;
     XilinxAXIDMAStreamSink rx_control_dev;
+    uint32_t flags;
 
     struct Stream streams[2];
 
@@ -168,6 +177,11 @@ static inline int stream_idle(struct Stream *s)
     return !!(s->regs[R_DMASR] & DMASR_IDLE);
 }
 
+static inline int stream_halted(struct Stream *s)
+{
+    return !!(s->regs[R_DMASR] & DMASR_HALTED);
+}
+
 static void stream_reset(struct Stream *s)
 {
     s->regs[R_DMASR] = DMASR_HALTED;  /* starts up halted.  */
@@ -185,15 +199,36 @@ static inline int streamid_from_addr(hwaddr addr)
     return sid;
 }
 
+static inline hwaddr stream_ptr_get(struct Stream *s, int base)
+{
+    if (s->dma->flags & XILINX_AXIDMA_FLAG_64BIT) {
+        return s->regs[base] | ((hwaddr)s->regs[base + 1] << 32);
+    } else {
+        return s->regs[base];
+    }
+}
+
+static inline void stream_ptr_set(struct Stream *s, int base, hwaddr addr)
+{
+    s->regs[base] = addr;
+    if (s->dma->flags & XILINX_AXIDMA_FLAG_64BIT)
+        s->regs[base + 1] = addr >> 32;
+}
+
 static void stream_desc_load(struct Stream *s, hwaddr addr)
 {
     struct SDesc *d = &s->desc;
 
     address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
 
     /* Convert from LE into host endianness.  */
-    d->buffer_address = le64_to_cpu(d->buffer_address);
-    d->nxtdesc = le64_to_cpu(d->nxtdesc);
+    if (s->dma->flags & XILINX_AXIDMA_FLAG_64BIT) {
+        d->buffer_address = le64_to_cpu(d->buffer_address);
+        d->nxtdesc = le64_to_cpu(d->nxtdesc);
+    } else {
+        d->buffer_address = le32_to_cpu(*(uint32_t *)&d->buffer_address);
+        d->nxtdesc = le32_to_cpu(*(uint32_t *)&d->nxtdesc);
+    }
     d->control = le32_to_cpu(d->control);
     d->status = le32_to_cpu(d->status);
 }
@@ -264,17 +299,17 @@ static void stream_complete(struct Stream *s)
 static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
                                  StreamSink *tx_control_dev)
 {
-    uint32_t prev_d;
-    uint32_t txlen;
+    uint64_t prev_d;
+    uint32_t orig_txlen, txlen;
     uint64_t addr;
     bool eop;
 
-    if (!stream_running(s) || stream_idle(s)) {
+    if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
         return;
     }
 
     while (1) {
-        stream_desc_load(s, s->regs[R_CURDESC]);
+        stream_desc_load(s, stream_ptr_get(s, R_CURDESC));
 
         if (s->desc.status & SDESC_STATUS_COMPLETE) {
             s->regs[R_DMASR] |= DMASR_HALTED;
@@ -285,7 +320,7 @@ static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
             stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app), true);
         }
 
-        txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
+        orig_txlen = txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
 
         eop = stream_desc_eof(&s->desc);
         addr = s->desc.buffer_address;
@@ -306,13 +341,13 @@ static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
         }
 
         /* Update the descriptor.  */
-        s->desc.status = txlen | SDESC_STATUS_COMPLETE;
-        stream_desc_store(s, s->regs[R_CURDESC]);
+        s->desc.status = orig_txlen | SDESC_STATUS_COMPLETE;
+        stream_desc_store(s, stream_ptr_get(s, R_CURDESC));
 
         /* Advance.  */
-        prev_d = s->regs[R_CURDESC];
-        s->regs[R_CURDESC] = s->desc.nxtdesc;
-        if (prev_d == s->regs[R_TAILDESC]) {
+        prev_d = stream_ptr_get(s, R_CURDESC);
+        stream_ptr_set(s, R_CURDESC, s->desc.nxtdesc);
+        if (prev_d == stream_ptr_get(s, R_TAILDESC)) {
             s->regs[R_DMASR] |= DMASR_IDLE;
             break;
         }
@@ -322,16 +357,16 @@ static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
 static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
                                    size_t len, bool eop)
 {
-    uint32_t prev_d;
+    uint64_t prev_d;
     unsigned int rxlen;
     size_t pos = 0;
 
-    if (!stream_running(s) || stream_idle(s)) {
+    if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
         return 0;
     }
 
     while (len) {
-        stream_desc_load(s, s->regs[R_CURDESC]);
+        stream_desc_load(s, stream_ptr_get(s, R_CURDESC));
 
         if (s->desc.status & SDESC_STATUS_COMPLETE) {
             s->regs[R_DMASR] |= DMASR_HALTED;
@@ -358,13 +393,13 @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
 
         s->desc.status |= s->sof << SDESC_STATUS_SOF_BIT;
         s->desc.status |= SDESC_STATUS_COMPLETE;
-        stream_desc_store(s, s->regs[R_CURDESC]);
+        stream_desc_store(s, stream_ptr_get(s, R_CURDESC));
         s->sof = eop;
 
         /* Advance.  */
-        prev_d = s->regs[R_CURDESC];
-        s->regs[R_CURDESC] = s->desc.nxtdesc;
-        if (prev_d == s->regs[R_TAILDESC]) {
+        prev_d = stream_ptr_get(s, R_CURDESC);
+        stream_ptr_set(s, R_CURDESC, s->desc.nxtdesc);
+        if (prev_d == stream_ptr_get(s, R_TAILDESC)) {
             s->regs[R_DMASR] |= DMASR_IDLE;
             break;
         }
@@ -407,7 +442,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
     XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
     struct Stream *s = &ds->dma->streams[1];
 
-    if (!stream_running(s) || stream_idle(s)) {
+    if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
         ds->dma->notify = notify;
         ds->dma->notify_opaque = notify_opaque;
         return false;
@@ -502,12 +537,22 @@ static void axidma_write(void *opaque, hwaddr addr,
             break;
 
         case R_TAILDESC:
+        case R_TAILDESC_MSB:
+            if ((addr == R_TAILDESC_MSB) &&
+                !(s->dma->flags & XILINX_AXIDMA_FLAG_64BIT))
+                break;
+
             s->regs[addr] = value;
+            if ((addr == R_TAILDESC) &&
+                (s->dma->flags & XILINX_AXIDMA_FLAG_64BIT))
+                break;
+
             s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle.  */
             if (!sid) {
                 stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev);
             }
             break;
+
         default:
             D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
                   __func__, sid, addr * 4, (unsigned)value));
@@ -591,6 +636,8 @@ static Property axidma_properties[] = {
                      tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
     DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
                      tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
+    DEFINE_PROP_BIT("64bit", XilinxAXIDMA, flags,
+                    XILINX_AXIDMA_FLAG_64BIT_BIT, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 

hw/gpio/Kconfig

@@ -13,3 +13,7 @@ config GPIO_PWR
 
 config SIFIVE_GPIO
     bool
+
+config XILINX_AXI_GPIO
+    bool
+    select REGISTER

hw/gpio/meson.build

@@ -12,3 +12,4 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
+softmmu_ss.add(when: 'CONFIG_XILINX_AXI_GPIO', if_true: files('xilinx-axi-gpio.c'))