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add test
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‎tests/test_gpio.py‎

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# amaranth: UnusedElaboratable=no
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import unittest
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from amaranth import *
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from amaranth.sim import *
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from amaranth_orchard.io import GPIOPeripheral
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class PeripheralTestCase(unittest.TestCase):
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def test_init(self):
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dut_1 = GPIOPeripheral(pin_count=4, addr_width=2, data_width=8)
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self.assertEqual(dut_1.pin_count, 4)
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self.assertEqual(dut_1.input_stages, 2)
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self.assertEqual(dut_1.bus.addr_width, 2)
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self.assertEqual(dut_1.bus.data_width, 8)
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dut_2 = GPIOPeripheral(pin_count=1, addr_width=8, data_width=16, input_stages=3)
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self.assertEqual(dut_2.pin_count, 1)
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self.assertEqual(dut_2.input_stages, 3)
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self.assertEqual(dut_2.bus.addr_width, 8)
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self.assertEqual(dut_2.bus.data_width, 16)
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def test_init_wrong_pin_count(self):
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with self.assertRaisesRegex(TypeError,
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r"Pin count must be a positive integer, not 'foo'"):
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GPIOPeripheral(pin_count="foo", addr_width=2, data_width=8)
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with self.assertRaisesRegex(TypeError,
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r"Pin count must be a positive integer, not 0"):
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GPIOPeripheral(pin_count=0, addr_width=2, data_width=8)
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def test_init_wrong_input_stages(self):
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with self.assertRaisesRegex(TypeError,
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r"Input stages must be a non-negative integer, not 'foo'"):
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GPIOPeripheral(pin_count=1, addr_width=2, data_width=8, input_stages="foo")
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with self.assertRaisesRegex(TypeError,
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r"Input stages must be a non-negative integer, not -1"):
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GPIOPeripheral(pin_count=1, addr_width=2, data_width=8, input_stages=-1)
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async def _csr_access(self, ctx, dut, addr, r_stb=0, w_stb=0, w_data=0, r_data=0):
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ctx.set(dut.bus.addr, addr)
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ctx.set(dut.bus.r_stb, r_stb)
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ctx.set(dut.bus.w_stb, w_stb)
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ctx.set(dut.bus.w_data, w_data)
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await ctx.tick()
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if r_stb:
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self.assertEqual(ctx.get(dut.bus.r_data), r_data)
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ctx.set(dut.bus.r_stb, 0)
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ctx.set(dut.bus.w_stb, 0)
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def test_sim(self):
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dut = GPIOPeripheral(pin_count=4, addr_width=2, data_width=8)
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mode_addr = 0x0
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input_addr = 0x1
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output_addr = 0x2
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setclr_addr = 0x3
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async def testbench(ctx):
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# INPUT_ONLY mode =====================================================================
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# - read Mode:
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await self._csr_access(ctx, dut, mode_addr, r_stb=1, r_data=0b00000000)
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self.assertEqual(ctx.get(dut.alt_mode), 0b0000)
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b0000)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b0000)
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# - read Input:
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ctx.set(dut.pins.gpio.i[1], 1)
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ctx.set(dut.pins.gpio.i[3], 1)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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ctx.set(dut.pins.gpio.i[1], 0)
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ctx.set(dut.pins.gpio.i[3], 0)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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# - write 0xf to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b0000)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b1111)
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# - write 0x22 to SetClr (clear pins[0] and pins[2]):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x22)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b0000)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b1010)
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# - write 0x0 to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b0000)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b0000)
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# - write 0x44 to SetClr (set pins[1] and pins[3]):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x44)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b0000)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b1010)
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# - write 0x0 to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b0000)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b0000)
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# - write 0xff to SetClr (no-op):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0xff)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b0000)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b0000)
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# PUSH_PULL mode ======================================================================
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# - write Mode:
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await self._csr_access(ctx, dut, mode_addr, w_stb=1, w_data=0b01010101)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.alt_mode), 0b0000)
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b1111)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b0000)
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# - read Input:
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ctx.set(dut.pins.gpio.i[1], 1)
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ctx.set(dut.pins.gpio.i[3], 1)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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ctx.set(dut.pins.gpio.i[1], 0)
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ctx.set(dut.pins.gpio.i[3], 0)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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# - write 0xf to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b1111)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b1111)
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# - write 0x22 to SetClr (clear pins[0] and pins[2]):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x22)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b1111)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b1010)
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# - write 0x0 to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b1111)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b1111)
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# - write 0x44 to SetClr (set pins[1] and pins[3]):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x44)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b1111)
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self.assertEqual(ctx.get(dut.pins.gpio.o), 0b1010)
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"""
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# - write 0x0 to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 1)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - write 0xff to SetClr (no-op):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0xff)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 1)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# OPEN_DRAIN mode =====================================================================
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# - write Mode:
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await self._csr_access(ctx, dut, mode_addr, w_stb=1, w_data=0b10101010)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.alt_mode[n]), 0)
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self.assertEqual(ctx.get(dut.pins[n].oe), 1)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - read Input:
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ctx.set(dut.pins[1].i, 1)
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ctx.set(dut.pins[3].i, 1)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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ctx.set(dut.pins[1].i, 0)
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ctx.set(dut.pins[3].i, 0)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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# - write 0xf to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 0)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - write 0x22 to SetClr (clear pins[0] and pins[2]):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x22)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins[0].oe), 1)
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self.assertEqual(ctx.get(dut.pins[1].oe), 0)
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self.assertEqual(ctx.get(dut.pins[2].oe), 1)
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self.assertEqual(ctx.get(dut.pins[3].oe), 0)
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - write 0x0 to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 1)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - write 0x44 to SetClr (set pins[1] and pins[3]):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x44)
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await ctx.tick()
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self.assertEqual(ctx.get(dut.pins[0].oe), 1)
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self.assertEqual(ctx.get(dut.pins[1].oe), 0)
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self.assertEqual(ctx.get(dut.pins[2].oe), 1)
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self.assertEqual(ctx.get(dut.pins[3].oe), 0)
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - write 0x0 to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 1)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - write 0xff to SetClr (no-op):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0xff)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 1)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# ALTERNATE mode ======================================================================
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# - write Mode:
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await self._csr_access(ctx, dut, mode_addr, w_stb=1, w_data=0b11111111)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.alt_mode[n]), 1)
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self.assertEqual(ctx.get(dut.pins[n].oe), 0)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - read Input:
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ctx.set(dut.pins[1].i, 1)
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ctx.set(dut.pins[3].i, 1)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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ctx.set(dut.pins[1].i, 0)
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ctx.set(dut.pins[3].i, 0)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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# - write 0xf to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0x0, w_stb=1, w_data=0xf)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 0)
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self.assertEqual(ctx.get(dut.pins[n].o), 1)
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# - write 0x22 to SetClr (clear pins[0] and pins[2]):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x22)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 0)
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self.assertEqual(ctx.get(dut.pins[0].o), 0)
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self.assertEqual(ctx.get(dut.pins[1].o), 1)
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self.assertEqual(ctx.get(dut.pins[2].o), 0)
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self.assertEqual(ctx.get(dut.pins[3].o), 1)
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# - write 0x0 to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 0)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - write 0x44 to SetClr (set pins[1] and pins[3]):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x44)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 0)
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self.assertEqual(ctx.get(dut.pins[0].o), 0)
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self.assertEqual(ctx.get(dut.pins[1].o), 1)
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self.assertEqual(ctx.get(dut.pins[2].o), 0)
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self.assertEqual(ctx.get(dut.pins[3].o), 1)
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# - write 0x0 to Output:
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await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 0)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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# - write 0xff to SetClr (no-op):
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await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0xff)
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await ctx.tick()
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for n in range(4):
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self.assertEqual(ctx.get(dut.pins[n].oe), 0)
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self.assertEqual(ctx.get(dut.pins[n].o), 0)
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"""
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sim = Simulator(dut)
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sim.add_clock(1e-6)
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sim.add_testbench(testbench)
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with sim.write_vcd(vcd_file="test.vcd"):
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sim.run()
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def test_sim_without_input_sync(self):
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dut = GPIOPeripheral(pin_count=4, addr_width=2, data_width=8, input_stages=0)
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input_addr = 0x1
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async def testbench(ctx):
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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ctx.set(dut.pins.gpio.i[1], 1)
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ctx.set(dut.pins.gpio.i[3], 1)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0xa)
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ctx.set(dut.pins.gpio.i[1], 0)
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ctx.set(dut.pins.gpio.i[3], 0)
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await self._csr_access(ctx, dut, input_addr, r_stb=1, r_data=0x0)
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sim = Simulator(dut)
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sim.add_clock(1e-6)
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sim.add_testbench(testbench)
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with sim.write_vcd(vcd_file="test.vcd"):
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sim.run()

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