wip

Author: robtaylor

amaranth_orchard/io/gpio.py

@@ -70,7 +70,7 @@ def __init__(self, *, pin_count, addr_width=4, data_width=4, input_stages=2):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules._gpio = self._gpio
+        m.submodules._gpio = gpio = self._gpio
 
         connect(m, flipped(self.bus), self._gpio.bus)
         for i in range(self._gpio.pin_count):

amaranth_orchard/memory/hyperram.py

@@ -5,7 +5,7 @@
 # Copyright (c) 2021-2022 gatecat <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
-from amaranth import Module, ClockSignal, ResetSignal, Signal, unsigned, ClockDomain
+from amaranth import Module, ClockSignal, ResetSignal, Signal, unsigned, ClockDomain, Cat
 from amaranth.lib import wiring
 from amaranth.lib.wiring import In, Out, connect, flipped
 from amaranth.utils import ceil_log2
@@ -46,9 +46,8 @@ class HRAMConfig(csr.Register, access="w"):
 
     This core favors portability and ease of use over performance.
     """
-    def __init__(self, mem_name=("mem",), *, pins, init_latency=7):
-        self.pins = pins
-        self.cs_count = pins.cs_count
+    def __init__(self, mem_name=("mem",), *, cs_count=1, init_latency=7):
+        self.cs_count = cs_count
         self.size = 2**23 * self.cs_count # 8MB per CS pin
         self.init_latency = init_latency
         assert self.init_latency in (6, 7) # TODO: anything else possible ?

tests/test_gpio.py

@@ -145,7 +145,7 @@ async def testbench(ctx):
             await self._csr_access(ctx, dut, output_addr, r_stb=1, r_data=0xa, w_stb=1, w_data=0x0)
             await ctx.tick()
             self.assertEqual(ctx.get(dut.pins.gpio.oe), 0b1111)
-            self.assertEqual(ctx.get(dut.pins.gpio.o), 0b1111)
+            self.assertEqual(ctx.get(dut.pins.gpio.o), 0b0000)
 
             # - write 0x44 to SetClr (set pins[1] and pins[3]):
             await self._csr_access(ctx, dut, setclr_addr, w_stb=1, w_data=0x44)