wip

Author: robtaylor

amaranth_orchard/base/gpio.py

@@ -12,10 +12,13 @@
 class GPIOPins(wiring.PureInterface):
     class Signature(wiring.Signature):
         def __init__(self, width):
+            if width > 32:
+                raise ValueError(f"Pin width must be lesser than or equal to 32, not {len(pins.o)}")
             self._width = width
-            super().__init__({
-                "o":  Out(BidirPinSignature(width)),
-            })
+            super().__init__(
+                # each pin has seperate output enable
+                {f"gpio{n}":Out(BidirPinSignature(1)) for n in range(width)}
+            )
 
         @property
         def width(self):
@@ -26,6 +29,10 @@ def create(self, *, path=(), src_loc_at=0):
 
     def __init__(self, width, *, path=(), src_loc_at=0):
         super().__init__(self.Signature(width), path=path, src_loc_at=1 + src_loc_at)
+    
+    @property  
+    def width(self):
+        return self.signature.width
 
 
 class GPIOPeripheral(wiring.Component):
@@ -49,10 +56,8 @@ def __init__(self, width):
     All pins default to input at power up.
     """
     def __init__(self, *, name, pins):
-        if len(pins.o) > 32:
-            raise ValueError(f"Pin width must be lesser than or equal to 32, not {len(pins.o)}")
 
-        self.width = len(pins.o)
+        self.width = pins.width
         self.pins  = pins
 
         regs = csr.Builder(addr_width=4, data_width=8, name=name)
@@ -74,10 +79,8 @@ def elaborate(self, platform):
 
         connect(m, flipped(self.bus), self._bridge.bus)
 
-        m.d.comb += [
-            self.pins.o .eq(self._do.f.pins.data),
-            self.pins.oe.eq(self._oe.f.pins.data),
-        ]
-        m.d.sync += self._di.f.pins.r_data.eq(self.pins.i)
+        m.d.comb += [ getattr(self.pins, f"gpio{n}").o.eq(self._do.f.pins.data[n]) for n in range(self.width)]
+        m.d.comb += [ getattr(self.pins, f"gpio{n}").oe.eq(self._oe.f.pins.data[n]) for n in range(self.width)]
+        m.d.comb += [ self._di.f.pins.r_data[n].eq(getattr(self.pins, f"gpio{n}").i) for n in range(self.width)]
 
         return m

amaranth_orchard/memory/spimemio.py

@@ -18,8 +18,8 @@ def __init__(self):
             super().__init__({
                 "clk": Out(OutputPinSignature(1)),
                 "csn": Out(OutputPinSignature(1)),
-                "d":   Out(BidirPinSignature(4)),
-            })
+            } |
+            {f"d{n}": Out(BidirPinSignature(1)) for n in range(4)})
 
         def create(self, *, path=(), src_loc_at=0):
             return QSPIPins(path=path, src_loc_at=1 + src_loc_at)
@@ -83,32 +83,28 @@ def elaborate(self, platform):
         spi_ready = Signal()
         # TODO : QSPI
 
-        m.submodules.spimemio = Instance(
-            "spimemio",
-            i_clk=ClockSignal(),
-            i_resetn=~ResetSignal(),
-            i_valid=self.data_bus.cyc & self.data_bus.stb,
-            o_ready=spi_ready,
-            i_addr=Cat(Const(0, 2), self.data_bus.adr), # Hack to force a 1MB offset
-            o_rdata=self.data_bus.dat_r,
-            o_flash_csb=self.flash.csn.o,
-            o_flash_clk=self.flash.clk.o,
-            o_flash_io0_oe=self.flash.d.oe[0],
-            o_flash_io1_oe=self.flash.d.oe[1],
-            o_flash_io2_oe=self.flash.d.oe[2],
-            o_flash_io3_oe=self.flash.d.oe[3],
-            o_flash_io0_do=self.flash.d.o[0],
-            o_flash_io1_do=self.flash.d.o[1],
-            o_flash_io2_do=self.flash.d.o[2],
-            o_flash_io3_do=self.flash.d.o[3],
-            i_flash_io0_di=self.flash.d.i[0],
-            i_flash_io1_di=self.flash.d.i[1],
-            i_flash_io2_di=self.flash.d.i[2],
-            i_flash_io3_di=self.flash.d.i[3],
-            i_cfgreg_we=ctrl_bridge.cfgreg_we,
-            i_cfgreg_di=ctrl_bridge.cfgreg_di,
-            o_cfgreg_do=ctrl_bridge.cfgreg_do,
-        )
+        verilog_map = {
+            "i_clk": ClockSignal(),
+            "i_resetn": ~ResetSignal(),
+            "i_valid": self.data_bus.cyc & self.data_bus.stb,
+            "o_ready": spi_ready,
+            "i_addr": Cat(Const(0, 2), self.data_bus.adr), # Hack to force a 1MB offset
+            "o_rdata": self.data_bus.dat_r,
+            "o_flash_csb": self.flash.csn.o,
+            "o_flash_clk": self.flash.clk.o,
+            "i_cfgreg_we": ctrl_bridge.cfgreg_we,
+            "i_cfgreg_di": ctrl_bridge.cfgreg_di,
+            "o_cfgreg_do": ctrl_bridge.cfgreg_do,
+        } | {
+            f"o_flash_io{n}_oe": getattr(self.flash, f"d{n}").oe for n in range(4)
+        } | {
+            f"o_flash_io{n}_o": getattr(self.flash, f"d{n}").o for n in range(4)
+        } | {
+            f"o_flash_io{n}_i": getattr(self.flash, f"d{n}").i for n in range(4) 
+        }
+ 
+        m.submodules.spimemio = Instance("spimemio", **verilog_map)
+
         # From https://github.com/im-tomu/foboot/blob/master/hw/rtl/picorvspi.py
         read_active = Signal()
         with m.If(self.data_bus.stb & self.data_bus.cyc & ~read_active):