Add GitHub Actions caching for ~/.cache directory

.github/workflows/main.yaml

@@ -31,9 +31,7 @@ jobs:
       - name: Check out source code
         uses: actions/checkout@v4
 
-      - uses: actions/setup-python@v4
-        with:
-          python-version: '3.10'
+      - uses: actions/setup-python@v5
 
       - name: Set up PDM
         uses: pdm-project/setup-pdm@v4
@@ -45,6 +43,15 @@ jobs:
       - name: Install dependencies with multirepo
         uses: chipflow/pdm-multirepo@v1
 
+      - name: Cache ~/.cache directory
+        uses: actions/cache@v4
+        with:
+          path: ~/.cache
+          key: cache-${{ runner.os }}-${{ matrix.design }}-${{ hashFiles('**/pyproject.toml', '**/pdm.lock') }}
+          restore-keys: |
+            cache-${{ runner.os }}-${{ matrix.design }}-
+            cache-${{ runner.os }}-
+
       - name: Lock pins
         working-directory: ./${{ matrix.design }}
         run: pdm run chipflow pin lock
@@ -76,13 +83,14 @@ jobs:
       - name: Install dependencies with multirepo
         uses: chipflow/pdm-multirepo@v1
 
-      - name: Cache YoWASP build products
+      - name: Cache ~/.cache directory
         uses: actions/cache@v4
         with:
-          path: ~/.cache/YoWASP
-          key: YoWASP-${{ runner.os }}-${{ hashFiles('./.venv/**/*.wasm') }}
+          path: ~/.cache
+          key: cache-${{ runner.os }}-${{ matrix.design }}-${{ hashFiles('**/pyproject.toml', '**/pdm.lock') }}
           restore-keys: |
-            YoWASP-${{ runner.os }}-
+            cache-${{ runner.os }}-${{ matrix.design }}-
+            cache-${{ runner.os }}-
 
       - name: Lock pins
         working-directory: ./${{ matrix.design }}

mcu_soc/design/design.py

@@ -13,7 +13,7 @@
 from amaranth_soc.wishbone.sram import WishboneSRAM
 from chipflow_digital_ip.io import GPIOPeripheral, UARTPeripheral, SPIPeripheral, I2CPeripheral
 from chipflow_digital_ip.processors import CV32E40P, OBIDebugModule
-from chipflow_lib.platforms import (
+from chipflow.platform import (
         GPIOSignature, UARTSignature, SPISignature, I2CSignature,
         QSPIFlashSignature, JTAGSignature,
         attach_data, SoftwareBuild

mcu_soc/design/ips/pdm.py

@@ -5,7 +5,7 @@
 from amaranth.lib.wiring import In, Out, flipped, connect
 from amaranth_soc import csr
 
-from chipflow_lib.platforms import OutputIOSignature, SoftwareDriverSignature
+from chipflow.platform import OutputIOSignature, SoftwareDriverSignature
 
 
 __all__ = ["PDMPeripheral"]

mcu_soc/design/ips/pwm.py

@@ -6,7 +6,7 @@
 from amaranth.lib.cdc import FFSynchronizer
 from amaranth_soc import csr
 
-from chipflow_lib.platforms import OutputIOSignature, InputIOSignature, SoftwareDriverSignature
+from chipflow.platform import OutputIOSignature, InputIOSignature, SoftwareDriverSignature
 
 __all__ = ["PWMPeripheral", "PWMPins"]
 

mcu_soc/design/software/doit_build.py

@@ -4,10 +4,10 @@
 import shutil
 
 from doit import create_after
-import chipflow_lib.config
+import chipflow.config
 
 
-CHIPFLOW_SOFTWARE_DIR = chipflow_lib.config.get_dir_software()
+CHIPFLOW_SOFTWARE_DIR = chipflow.config.get_dir_software()
 BUILD_DIR = "./build/software"
 DESIGN_DIR = os.path.dirname(__file__) + "/.."
 RISCVCC = f"{sys.executable} -m ziglang cc -target riscv32-freestanding-musl"

mcu_soc/design/steps/board.py

@@ -1,6 +1,6 @@
 from amaranth_boards.ulx3s import ULX3S_85F_Platform
 
-from chipflow_lib.steps.board import BoardStep
+from chipflow.platform import BoardStep
 
 from amaranth import *
 from amaranth.lib import wiring

mcu_soc/design/steps/sim.py

@@ -10,8 +10,8 @@
 
 from amaranth import *
 from amaranth.back import rtlil
-from chipflow_lib.steps.sim import SimStep
-from chipflow_lib import ChipFlowError
+from chipflow.platform import SimStep
+from chipflow import ChipFlowError
 
 from ..design import MySoC
 from ..sim.doit_build import VARIABLES, TASKS, DOIT_CONFIG
@@ -20,7 +20,7 @@
 
 @contextmanager
 def common():
-    chipflow_lib = importlib.resources.files('chipflow_lib')
+    chipflow_lib = importlib.resources.files('chipflow')
     common = chipflow_lib.joinpath('common', 'sim')
     with importlib.resources.as_file(common) as f:
         yield f

mcu_soc/design/steps/software.py

@@ -1,4 +1,4 @@
-from chipflow_lib.steps.software import SoftwareStep
+from chipflow.platform import SoftwareStep
 from ..software import doit_build
 
 

minimal/design/design.py

@@ -15,7 +15,7 @@
 
 from minerva.core import Minerva
 
-from chipflow_lib.platforms import Sky130DriveMode, GPIOSignature, UARTSignature, QSPIFlashSignature, attach_data, SoftwareBuild
+from chipflow.platform import Sky130DriveMode, GPIOSignature, UARTSignature, QSPIFlashSignature, attach_data, SoftwareBuild
 
 
 __all__ = ["MySoC"]

minimal/design/software/doit_build.py

@@ -4,10 +4,10 @@
 import shutil
 
 from doit import create_after
-import chipflow_lib.config
+import chipflow.config
 
 
-CHIPFLOW_SOFTWARE_DIR = chipflow_lib.config.get_dir_software()
+CHIPFLOW_SOFTWARE_DIR = chipflow.config.get_dir_software()
 BUILD_DIR = "./build/software"
 DESIGN_DIR = os.path.dirname(__file__) + "/.."
 RISCVCC = f"{sys.executable} -m ziglang cc -target riscv32-freestanding-musl"

minimal/design/steps/board.py

@@ -1,6 +1,6 @@
 from amaranth_boards.ulx3s import ULX3S_85F_Platform
 
-from chipflow_lib.steps.board import BoardStep
+from chipflow.platform import BoardStep
 
 from amaranth import *
 from amaranth.lib import wiring

minimal/design/steps/software.py

@@ -1,4 +1,4 @@
-from chipflow_lib.steps.software import SoftwareStep
+from chipflow.platform import SoftwareStep
 from ..software import doit_build