Clean up some issues

Author: robtaylor

chipflow_lib/platforms/utils.py

@@ -72,8 +72,19 @@ class VoltageRange:
     "required": ["width", "signed", "value"]
 })
 
-@with_config(ConfigDict(use_enum_values=True, arbitrary_types_allowed=True))  # type: ignore[reportCallIssue]
-class IOModel(TypedDict):
+
+@with_config(ConfigDict(arbitrary_types_allowed=True))  # type: ignore[reportCallIssue]
+class _IOModelOptions(TypedDict):
+    all_have_oe: NotRequired[bool]
+    allocate_power: NotRequired[bool]
+    power_voltage: NotRequired[VoltageRange]
+    clock_domain_i: NotRequired[str]
+    clock_domain_o: NotRequired[str]
+    init: NotRequired[Annotated[Const, ConstSerializer, ConstSchema]]
+
+
+@with_config(ConfigDict(arbitrary_types_allowed=True))  # type: ignore[reportCallIssue]
+class IOModel(_IOModelOptions):
     """
     Options for IO Ports
     Attributes:
@@ -89,19 +100,17 @@ class IOModel(TypedDict):
         init: a :ref:`Const` value for the initial values of the port
     """
 
-    width: NotRequired[int]
+    width: int
     direction: NotRequired[Annotated[io.Direction, PlainSerializer(lambda x: x.value)]]
-    all_have_oe: NotRequired[bool]
-    allocate_power: NotRequired[bool]
-    power_voltage: NotRequired[VoltageRange]
-    clock_domain_i: NotRequired[str]
-    clock_domain_o: NotRequired[str]
-    init: NotRequired[Annotated[Const, ConstSerializer, ConstSchema]]
-
 
 def io_annotation_schema():
+    class Model(pydantic.BaseModel):
+        data_td: IOModel
+    print(Model.model_json_schema())
+
     PydanticModel = TypeAdapter(IOModel)
-    schema = PydanticModel.json_schema()
+    #schema = PydanticModel.json_schema()
+    schema = Model.model_json_schema()
     schema['$schema'] = "https://json-schema.org/draft/2020-12/schema"
     schema['$id'] = IO_ANNOTATION_SCHEMA
     return schema
@@ -184,45 +193,37 @@ def __repr__(self):
         return f"IOSignature({','.join('{0}={1!r}'.format(k,v) for k,v in self._model.items())})"
 
 
-def OutputIOSignature(width: int, **kwargs: Unpack[IOModel]):  # type: ignore[reportGeneralTypeIssues]
+def OutputIOSignature(width: int, **kwargs: Unpack[_IOModelOptions]):
     """This creates an :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` which is then used to decorate package output signals
     intended for connection to the physical pads of the integrated circuit package.
 
     :param width: specifies the number of individual output wires within this port, each of which will correspond to a separate physical pad on the integrated circuit package.
-    :type width: int
-    :param init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port
     """
-    kwargs['width'] = width
-    kwargs['direction'] = io.Direction.Output
-    return IOSignature(**kwargs)
+    model: IOModel = kwargs | {'width': width, 'direction': io.Direction.Output}   # type: ignore[reportGeneralTypeIssues]
+    return IOSignature(**model)
 
 
-def InputIOSignature(width:int, **kwargs: Unpack[IOModel]):  # type: ignore[reportGeneralTypeIssues]
+def InputIOSignature(width: int, **kwargs: Unpack[_IOModelOptions]):  # type: ignore[reportGeneralTypeIssues]
     """This creates an :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` which is then used to decorate package input signals
     intended for connection to the physical pads of the integrated circuit package.
 
     :param width: specifies the number of individual input wires within this port, each of which will correspond to a separate physical pad on the integrated circuit package.
-    :type width: int
-    :param init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port
     """
-    kwargs['width'] = width
-    kwargs['direction'] = io.Direction.Input
-    return IOSignature(**kwargs)
+
+    model: IOModel = kwargs | {'width': width, 'direction': io.Direction.Input}   # type: ignore[reportGeneralTypeIssues]
+    return IOSignature(**model)
 
 
-def BidirIOSignature(width:int , **kwargs: Unpack[IOModel]):  # type: ignore[reportGeneralTypeIssues]
+def BidirIOSignature(width: int, **kwargs: Unpack[_IOModelOptions]):  # type: ignore[reportGeneralTypeIssues]
     """This creates an :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` which is then used to decorate package bi-directional signals
     intended for connection to the physical pads of the integrated circuit package.
 
     :param width: specifies the number of individual input/output wires within this port. Each pair of input/output wires will correspond to a separate physical pad on the integrated circuit package.
-    :type width: int
-    :param all_have_oe: controls whether each output wire is associated with an individual Output Enable bit or a single OE bit will be used for entire port, the default value is False, indicating that a single OE bit controls the entire port.
-    :type all_have_oe: bool, optional
-    :param init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port
     """
-    kwargs['width'] = width
-    kwargs['direction'] = io.Direction.Bidir
-    return IOSignature(**kwargs)
+
+
+    model: IOModel = kwargs | {'width': width, 'direction': io.Direction.Bidir}   # type: ignore[reportGeneralTypeIssues]
+    return IOSignature(**model)
 
 
 Pin = Union[Tuple[Any,...], str, int]
@@ -298,12 +299,13 @@ class Port(pydantic.BaseModel):
     type: str
     pins: List[Pin] | None  # None implies must be allocated at end
     port_name: str
-    direction: Optional[io.Direction] = None
-    options: Optional[dict] = None
+    iomodel: IOModel
 
     @property
     def width(self):
-        return len(self.pins) if self.pins else 0
+        assert self.pins and 'width' in self.iomodel
+        assert len(self.pins) == self.iomodel['width']
+        return self.iomodel['width']
 
 
 def _group_consecutive_items(ordering: PinList, lst: PinList) -> OrderedDict[int, List[PinList]]:
@@ -406,14 +408,11 @@ def _allocate_pins(name: str, member: Dict[str, Any], pins: List[Pin], port_name
 
     if member['type'] == 'interface' and 'annotations' in member \
        and IO_ANNOTATION_SCHEMA in member['annotations']:
-        logger.debug("matched IOSignature {sig}")
-        sig = member['annotations'][IO_ANNOTATION_SCHEMA]
-        logger.debug(f"matched PinSignature {sig}")
+        model:IOModel = member['annotations'][IO_ANNOTATION_SCHEMA]
+        logger.debug(f"matched IOSignature {model}")
         name = name
-        width = sig['width']
-        pin_map[name] = {'pins': pins[0:width],
-                         'type': 'io',
-                         'port_name': port_name } | sig
+        width = model['width']
+        pin_map[name] = Port(pins=pins[0:width], type='io', port_name=port_name, iomodel=model)
         logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
         return pin_map, pins[width:]
     elif member['type'] == 'interface':
@@ -426,11 +425,8 @@ def _allocate_pins(name: str, member: Dict[str, Any], pins: List[Pin], port_name
     elif member['type'] == 'port':
         logger.warning(f"Port '{name}' has no IOSignature, pin allocation likely to be wrong")
         width = member['width']
-        pin_map[name] = {'pins': pins[0:width],
-                              'direction': member['dir'],
-                              'type': 'io',
-                              'port_name': port_name
-                              }
+        model = IOModel(width=width, direction=io.Direction(member['dir']))
+        pin_map[name] = Port(pins=pins[0:width], type='io', port_name=port_name, iomodel=model)
         logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
         return pin_map, pins[width:]
     else: