wip

Author: robtaylor

chipflow_lib/config_models.py

@@ -1,12 +1,11 @@
 # SPDX-License-Identifier: BSD-2-Clause
 import re
-from typing import Dict, Optional, Literal, Any
+from typing import Dict, Optional, Literal, Any, List
 
 from pydantic import BaseModel, model_validator, ValidationInfo, field_validator
 
 from .platforms.utils import Process
 
-
 class PadConfig(BaseModel):
     """Configuration for a pad in chipflow.toml."""
     type: Literal["io", "i", "o", "oe", "clock", "reset", "power", "ground"]
@@ -72,8 +71,7 @@ class ChipFlowConfig(BaseModel):
     top: Dict[str, Any] = {}
     steps: Optional[Dict[str, str]] = None
     silicon: Optional[SiliconConfig] = None
-    clocks: Optional[Dict[str, str]] = None
-    resets: Optional[Dict[str, str]] = None
+    clock_domains: Optional[List[str]] = None
 
 
 class Config(BaseModel):

chipflow_lib/platforms/silicon.py

@@ -73,7 +73,7 @@ def __init__(self,
                  invert: bool = False):
         self._direction = io.Direction(port.direction)
         self._invert = invert
-        self._options = port.options
+        self._model = port.model
         self._pins = port.pins
 
         # Initialize signal attributes to None

chipflow_lib/platforms/utils.py

@@ -14,14 +14,14 @@
 from typing import (
     Any, Dict, List, Set,
     Tuple, Optional, Union, Literal,
-    Annotated, NamedTuple
+    Annotated, NamedTuple, Self
 )
 from typing_extensions import (
     TypedDict, Unpack, NotRequired
 )
 
 
-from amaranth import Const
+from amaranth import Const, ClockDomain, Fragment
 from amaranth.lib import wiring, io, meta
 from amaranth.lib.wiring import In, Out
 from pydantic import (
@@ -72,7 +72,7 @@ class VoltageRange:
     "required": ["width", "signed", "value"]
 })
 
-@with_config(ConfigDict(use_enum_values=True, arbitrary_types_allowed=True))
+@with_config(ConfigDict(use_enum_values=True, arbitrary_types_allowed=True))  # type: ignore[reportCallIssue]
 class IOModel(TypedDict):
     """
     Options for IO Ports
@@ -82,8 +82,10 @@ class IOModel(TypedDict):
         all_have_oe: controls whether each output wire is associated with an individual Output Enable bit
             or a single OE bit will be used for entire port, the default value is False, indicating that a
             single OE bit controls the entire port.
-        allocate_power: Whether a power line should be allocated with this interface
+        allocate_power: Whether a power line should be allocated with this interface.  NB there is only one of these, so IO with multiple IO power domains must be split up.
         power_voltage: Voltage range of the allocated power
+        clock_domain_i: the name of the `Amaranth.ClockDomain` for input. NB there is only one of these, so IO with multiple input clocks must be split up.
+        clock_domain_o: the name of the `Amaranth.ClockDomain` for output. NB there is only one of these, so IO with multiple output clocks must be split up.
         init: a :ref:`Const` value for the initial values of the port
     """
 
@@ -92,8 +94,11 @@ class IOModel(TypedDict):
     all_have_oe: NotRequired[bool]
     allocate_power: NotRequired[bool]
     power_voltage: NotRequired[VoltageRange]
+    clock_domain_i: NotRequired[str]
+    clock_domain_o: NotRequired[str]
     init: NotRequired[Annotated[Const, ConstSerializer, ConstSchema]]
 
+
 def io_annotation_schema():
     PydanticModel = TypeAdapter(IOModel)
     schema = PydanticModel.json_schema()
@@ -144,6 +149,12 @@ def __init__(self, **kwargs: Unpack[IOModel]):
                 sig = {"o": Out(width)}
             case _:
                 assert False
+
+        if 'clock_domain_i' not in model:
+            model['clock_domain_i'] = 'sync'
+        if 'clock_domain_o' not in model:
+            model['clock_domain_o'] = 'sync'
+
         self._model = model
         super().__init__(sig)
 
@@ -382,7 +393,7 @@ def _count_member_pins(name: str, member: Dict[str, Any]) -> int:
     return 0
 
 
-def _allocate_pins(name: str, member: Dict[str, Any], pins: List[str], port_name: Optional[str] = None) -> Tuple[Dict[str, Port], List[str]]:
+def _allocate_pins(name: str, member: Dict[str, Any], pins: List[Pin], port_name: Optional[str] = None) -> Tuple[Dict[str, Port], List[Pin]]:
     "Allocate pins based of Amaranth member metadata"
 
     if port_name is None:
@@ -459,7 +470,7 @@ class LockFile(pydantic.BaseModel):
     Representation of a pin lock file.
 
     Attributes:
-        package: Information about package, power, clocks, reset etc
+        package: Information about the physical package
         port_map: Mapping of components to interfaces to port
         metadata: Amaranth metadata, for reference
     """
@@ -474,9 +485,10 @@ class LockFile(pydantic.BaseModel):
 class Package(pydantic.BaseModel):
     """
     Serialisable identifier for a defined packaging option
+    Attributes:
+        type: Package type
     """
     type: PackageDef = pydantic.Field(discriminator="package_type")
-    clocks: List[str]
 
 def _linear_allocate_components(interfaces: dict, lockfile: LockFile | None, allocate, unallocated) -> PortMap:
     port_map = PortMap()
@@ -528,7 +540,8 @@ class BasePackageDef(pydantic.BaseModel, abc.ABC):
     name: str
 
     def model_post_init(self, __context):
-        self._interfaces = {}
+        self._interfaces: Dict[str, dict] = {}
+        self._components: Dict[str, wiring.Component] = {}
         return super().model_post_init(__context)
 
     def register_component(self, name: str, component: wiring.Component) -> None:
@@ -539,8 +552,12 @@ def register_component(self, name: str, component: wiring.Component) -> None:
             component: Amaranth `wiring.Component` to allocate
 
         """
+        self._components[name] = component
         self._interfaces[name] = component.metadata.as_json()
 
+    def _get_package(self) -> Package:
+        assert self is not Self
+        return Package(type=self)  # type: ignore
 
     @abc.abstractmethod
     def allocate_pins(self, process: 'Process', lockfile: Optional[LockFile]) -> LockFile:
@@ -595,8 +612,8 @@ def model_post_init(self, __context):
 
     def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> LockFile:
         portmap =  _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
-        #clocks = 
-        return LockFile(package=Package(type=self), process=process, metadata=self._interfaces, port_map=portmap)
+        package = self._get_package()
+        return LockFile(package=package, process=process, metadata=self._interfaces, port_map=portmap)
 
     @property
     def bringup_pins(self) -> BringupPins:
@@ -676,8 +693,8 @@ def model_post_init(self, __context):
 
     def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> 'LockFile':
         portmap = _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
-        return LockFile(package=Package(type=self), process=process, metadata=self._interfaces, port_map=portmap)
-
+        package = self._get_package()
+        return LockFile(package=package, process=process, metadata=self._interfaces, port_map=portmap)
 
     def _allocate(self, available: Set[int], width: int) -> List[Pin]:
         avail_n: List[Pin] = sorted(available)
@@ -888,7 +905,8 @@ def sort_by_quadrant(pins: Set[GAPin]) -> List[Pin]:
 
     def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> 'LockFile':
         portmap = _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
-        return LockFile(package=Package(type=self), process=process, metadata=self._interfaces, port_map=portmap)
+        package = self._get_package()
+        return LockFile(package=package, process=process, metadata=self._interfaces, port_map=portmap)
 
     def _allocate(self, available: Set[Pin], width: int) -> List[Pin]:
         avail_n = sorted(available)

chipflow_lib/steps/silicon.py

@@ -48,7 +48,7 @@ def elaborate(self, platform: SiliconPlatform):
         for n, t in top.items():
             setattr(m.submodules, n, t)
 
-        for component, iface in platform.pinlock.port_map.items():
+        for component, iface in platform.pinlock.port_map.ports.items():
             for iface_name, member, in iface.items():
                 for name, port in member.items():
                     iface = getattr(top[component], iface_name)
@@ -127,6 +127,11 @@ def submit(self, rtlil_path, args):
                 raise ChipFlowError(
                     "Environment variable `CHIPFLOW_API_KEY` is empty."
                 )
+        self._chipflow_api_origin = os.environ.get("CHIPFLOW_API_ORIGIN", "https://build.chipflow.org")
+
+        assert self._chipflow_api_key
+        assert self._chipflow_api_origin
+
         with  Halo(text="Submitting...", spinner="dots") as sp:
             fh = None
             submission_name = self.determine_submission_name()
@@ -176,18 +181,17 @@ def network_err(e):
                     fh.close()
                 exit(1)
 
-            sp.info(f"> Submitting {submission_name} for project {self.project_name} to ChipFlow Cloud {'('+os.environ.get('CHIPFLOW_API_ORIGIN')+')' if 'CHIPFLOW_API_ORIGIN' in os.environ else ''}")
+            sp.info(f"> Submitting {submission_name} for project {self.project_name} to ChipFlow Cloud {self._chipflow_api_origin}")
             sp.start("Sending design to ChipFlow Cloud")
 
-            chipflow_api_origin = os.environ.get("CHIPFLOW_API_ORIGIN", "https://build.chipflow.org")
-            build_submit_url = f"{chipflow_api_origin}/build/submit"
+            build_submit_url = f"{self._chipflow_api_origin}/build/submit"
 
             try:
                 resp = requests.post(
                     build_submit_url,
                     # TODO: This needs to be reworked to accept only one key, auth accepts user and pass
                     # TODO: but we want to submit a single key
-                    auth=(None, self._chipflow_api_key),
+                    auth=("", self._chipflow_api_key),
                     data=data,
                     files={
                         "rtlil": open(rtlil_path, "rb"),
@@ -207,14 +211,14 @@ def network_err(e):
             try:
                 resp_data = resp.json()
             except ValueError:
-                resp_data = resp.text
+                resp_data = {'message': resp.text}
 
             # Handle response based on status code
             if resp.status_code == 200:
                 logger.debug(f"Submitted design: {resp_data}")
-                self._build_url = f"{chipflow_api_origin}/build/{resp_data['build_id']}"
-                self._build_status_url = f"{chipflow_api_origin}/build/{resp_data['build_id']}/status"
-                self._log_stream_url = f"{chipflow_api_origin}/build/{resp_data['build_id']}/logs?follow=true"
+                self._build_url = f"{self._chipflow_api_origin}/build/{resp_data['build_id']}"
+                self._build_status_url = f"{self._chipflow_api_origin}/build/{resp_data['build_id']}/status"
+                self._log_stream_url = f"{self._chipflow_api_origin}/build/{resp_data['build_id']}/logs?follow=true"
 
                 sp.succeed("✅ Design submitted successfully! Build URL: {self._build_url}")
 
@@ -251,13 +255,14 @@ def network_err(e):
     def _long_poll_stream(self, sp, network_err):
         steps = self._last_log_steps
         stream_event_counter = 0
+        assert self._chipflow_api_key
         # after 4 errors, return to _stream_logs loop and query the build status again
         while (stream_event_counter < 4):
             sp.text = "Build running... " + ' -> '.join(steps)
             try:
                 log_resp = requests.get(
                     self._log_stream_url,
-                    auth=(None, self._chipflow_api_key),
+                    auth=("", self._chipflow_api_key),
                     stream=True,
                     timeout=(2.0, 60.0)  # fail if connect takes >2s, long poll for 60s at a time
                 )
@@ -284,18 +289,19 @@ def _long_poll_stream(self, sp, network_err):
                     logger.debug(f"Failed to stream logs: {log_resp.text}")
                     sp.text = "💥 Failed streaming build logs. Trying again!"
                     break
-            except requests.ConnectTimeout:
+            except requests.ConnectionError as e:
+                if type(e.__context__) is urllib3.exceptions.ReadTimeoutError:
+                    continue  #just timed out, continue long poll
                 sp.text = "💥 Failed connecting to ChipFlow Cloud."
                 logger.debug(f"Error while streaming logs: {e}")
                 break
             except (requests.RequestException, requests.exceptions.ReadTimeout) as e:
+                if type(e.__context__) is urllib3.exceptions.ReadTimeoutError:
+                    continue  #just timed out, continue long poll
                 sp.text = "💥 Failed streaming build logs. Trying again!"
                 logger.debug(f"Error while streaming logs: {e}")
                 stream_event_counter +=1
                 continue
-            except requests.ConnectionError as e:
-                if type(e.__context__) is urllib3.exceptions.ReadTimeoutError:
-                    continue  #just timed out, continue long poll
 
         # save steps so we coninue where we left off if we manage to reconnect
         self._last_log_steps = steps
@@ -309,13 +315,14 @@ def _stream_logs(self, sp, network_err):
         build_status = "pending"
         stream_event_counter = 0
         self._last_log_steps = []
+        assert self._chipflow_api_key is not None
         while fail_counter < 10 and stream_event_counter < 10:
             sp.text = f"Waiting for build to run... {build_status}"
             time.sleep(timeout)  # Wait before polling
             try:
                 status_resp = requests.get(
                     self._build_status_url,
-                    auth=(None, self._chipflow_api_key),
+                    auth=("", self._chipflow_api_key),
                     timeout=timeout
                 )
             except (requests.ConnectTimeout, requests.ConnectionError, requests.ConnectTimeout) as e: