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1 parent c6c730b commit 107d1d7Copy full SHA for 107d1d7
chipflow_lib/platforms/silicon.py
@@ -11,7 +11,7 @@
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from pprint import pformat
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from typing import TYPE_CHECKING, List
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-from amaranth import Module, Signal, ClockDomain, ClockSignal, ResetSignal, Value, unsigned
+from amaranth import Module, Signal, ClockDomain, ClockSignal, ResetSignal, unsigned
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from amaranth.lib import wiring, io, data
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from amaranth.lib.cdc import FFSynchronizer
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from amaranth.lib.wiring import Component, In, PureInterface
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