44import pathlib
55import pydantic
66
7- from collections import OrderedDict , deque
7+ from collections import OrderedDict , deque , defaultdict
88from collections .abc import Iterable
99from pprint import pformat
1010from typing import Set , List , Dict , Optional , Union , Literal , Tuple
@@ -655,8 +655,26 @@ def _allocate_bringup(self, config: 'Config') -> Component:
655655 port_name = 'rst_n' ,
656656 iomodel = IOModel (width = 1 , direction = io .Direction .Input , clock_domain = "sync" ,
657657 invert = True )
658- )
658+ ),
659+
659660 }
661+
662+ powerpins = defaultdict (list )
663+ for pp in self .bringup_pins .core_power :
664+ vss = "vss"
665+ vdd = "vdd"
666+ if pp .name :
667+ vss = f"vss{ pp .name } "
668+ vdd = f"vdd{ pp .name } "
669+ powerpins [vss ].append (pp .power )
670+ powerpins [vdd ].append (pp .ground )
671+
672+ for domain , pins in powerpins .items ():
673+ d [domain ] = PortDesc (type = 'power' ,
674+ pins = pins ,
675+ port_name = domain ,
676+ iomodel = IOModel (width = len (pins ), direction = io .Direction .Input ))
677+
660678 assert config .chipflow .silicon
661679 if config .chipflow .silicon .debug and \
662680 config .chipflow .silicon .debug ['heartbeat' ]:
@@ -665,6 +683,7 @@ def _allocate_bringup(self, config: 'Config') -> Component:
665683 port_name = 'heartbeat' ,
666684 iomodel = IOModel (width = 1 , direction = io .Direction .Output , clock_domain = "sync" )
667685 )
686+
668687 #TODO: JTAG
669688 return {'bringup_pins' : d }
670689
@@ -682,6 +701,7 @@ def allocate_pins(self, config: 'Config', process: 'Process', lockfile: LockFile
682701 ...
683702
684703 @property
704+ @abc .abstractmethod
685705 def bringup_pins (self ) -> BringupPins :
686706 """
687707 To aid bringup, these are always in the same place for each package type.
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