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Allocate power pins
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chipflow_lib/platforms/_utils.py

Lines changed: 22 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
import pathlib
55
import pydantic
66

7-
from collections import OrderedDict, deque
7+
from collections import OrderedDict, deque, defaultdict
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from collections.abc import Iterable
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from pprint import pformat
1010
from typing import Set, List, Dict, Optional, Union, Literal, Tuple
@@ -655,8 +655,26 @@ def _allocate_bringup(self, config: 'Config') -> Component:
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port_name='rst_n',
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iomodel=IOModel(width=1, direction=io.Direction.Input, clock_domain="sync",
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invert=True)
658-
)
658+
),
659+
659660
}
661+
662+
powerpins = defaultdict(list)
663+
for pp in self.bringup_pins.core_power:
664+
vss = "vss"
665+
vdd = "vdd"
666+
if pp.name:
667+
vss = f"vss{pp.name}"
668+
vdd = f"vdd{pp.name}"
669+
powerpins[vss].append(pp.power)
670+
powerpins[vdd].append(pp.ground)
671+
672+
for domain, pins in powerpins.items():
673+
d[domain] = PortDesc(type='power',
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pins=pins,
675+
port_name=domain,
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iomodel=IOModel(width=len(pins), direction=io.Direction.Input))
677+
660678
assert config.chipflow.silicon
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if config.chipflow.silicon.debug and \
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config.chipflow.silicon.debug['heartbeat']:
@@ -665,6 +683,7 @@ def _allocate_bringup(self, config: 'Config') -> Component:
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port_name='heartbeat',
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iomodel=IOModel(width=1, direction=io.Direction.Output, clock_domain="sync")
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)
686+
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#TODO: JTAG
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return {'bringup_pins': d}
670689

@@ -682,6 +701,7 @@ def allocate_pins(self, config: 'Config', process: 'Process', lockfile: LockFile
682701
...
683702

684703
@property
704+
@abc.abstractmethod
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def bringup_pins(self) -> BringupPins:
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"""
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To aid bringup, these are always in the same place for each package type.

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