fix lint issues

Author: robtaylor

chipflow_lib/_appresponse.py

@@ -32,7 +32,7 @@ def _serialize(self):
             # Run Annotated PlainSerializer
             for metadata in self.model_fields[name].metadata:
                 if isinstance(metadata, PlainSerializer):
-                    value = metadata.func(value)
+                    value = metadata.func(value)  # type: ignore
 
             serialized[serialize_key] = value
 

chipflow_lib/platforms/_internal.py

@@ -5,7 +5,7 @@
 __all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature', 'IOModel',
            'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
            'load_pinlock', "PACKAGE_DEFINITIONS", 'top_components', 'LockFile',
-           'Package', 'PortMap', 'Port', 'Process',
+           'Package', 'PortMap', 'PortDesc', 'Process',
            'GAPackageDef', 'QuadPackageDef', 'BareDiePackageDef', 'BasePackageDef',
            'BringupPins', 'JTAGPins', 'PowerPins',
            'SiliconPlatformPort', 'SiliconPlatform',

chipflow_lib/platforms/_packages.py

@@ -1,4 +1,4 @@
-from .utils import QuadPackageDef, BareDiePackageDef, GAPackageDef, Package
+from .utils import QuadPackageDef, BareDiePackageDef, Package
 from ._openframe import OpenframePackageDef
 
 # Add any new package types to both PACKAGE_DEFINITIONS and the PackageDef union

chipflow_lib/platforms/silicon.py

@@ -8,15 +8,15 @@
 
 from dataclasses import dataclass
 from pprint import pformat
-from typing import TYPE_CHECKING, List, Dict
+from typing import TYPE_CHECKING, List
 
-from amaranth import Module, Signal, Cat, ClockDomain, ClockSignal, ResetSignal
+from amaranth import Module, Signal, ClockDomain, ClockSignal, ResetSignal
 
 from amaranth.lib import wiring, io
 from amaranth.lib.cdc import FFSynchronizer
 from amaranth.lib.wiring import Component, In, PureInterface
 
-from amaranth.back import rtlil
+from amaranth.back import rtlil  #type: ignore[reportAttributeAccessIssue]
 from amaranth.hdl import Fragment
 from amaranth.hdl._ir import PortDirection
 
@@ -63,7 +63,7 @@ def elaborate(self, platform):
         heartbeat_ctr = Signal(self.counter_size)
         getattr(m.d, self.clock_domain).__iadd__(heartbeat_ctr.eq(heartbeat_ctr + 1))
 
-        heartbeat_buffer = io.Buffer("o", self.ports.heartbeat)
+        heartbeat_buffer = io.Buffer(io.Direction.Output, self.ports.heartbeat)
         m.submodules.heartbeat_buffer = heartbeat_buffer
         m.d.comb += heartbeat_buffer.o.eq(heartbeat_ctr[-1])  # type: ignore
         return m
@@ -240,10 +240,10 @@ def __init__(self,
         self._ie = None
 
         if self._oe is not None:
-            self._oe_n = Signal(self._oe.width, name=f"{self._name}$oeb")
+            self._oe_n = Signal(self._oe.shape().width, name=f"{self._name}$oeb")
             self._signals.append((self._oe_n, PortDirection.Output))
         if self._i is not None:
-            self._ie = Signal(self._i.width, name=f"{self._name}$inp_dis")
+            self._ie = Signal(self._i.shape().width, name=f"{self._name}$inp_dis")
             self._signals.append((self._ie, PortDirection.Input))
 
         # Port Configuration
@@ -387,7 +387,7 @@ def elaborate(self, platform):
 class SiliconPlatform:
     def __init__(self, config: 'Config'):
         if not config.chipflow.silicon:
-            raise ChipFlowError(f"I can't build for silicon without a [chipflow.silicon] section to guide me!")
+            raise ChipFlowError("I can't build for silicon without a [chipflow.silicon] section to guide me!")
         self._config = config
         self._ports = {}
         self._files = {}
@@ -411,16 +411,16 @@ def instantiate_ports(self, m: Module):
         print(pformat(self._ports))
         for clock in pinlock.port_map.get_clocks():
             assert 'clock_domain' in clock.iomodel
-            domain = name=clock.iomodel['clock_domain']
+            domain = clock.iomodel['clock_domain']
             setattr(m.domains, domain, ClockDomain(name=domain))
-            clk_buffer = io.Buffer("i", self._ports[clock.port_name])
+            clk_buffer = io.Buffer(io.Direction.Input, self._ports[clock.port_name])
             setattr(m.submodules, "clk_buffer_" + domain, clk_buffer)
             m.d.comb += ClockSignal().eq(clk_buffer.i)  #type: ignore[reportAttributeAccessIssue]
 
         for reset in pinlock.port_map.get_resets():
             assert 'clock_domain' in reset.iomodel
-            domain = name=reset.iomodel['clock_domain']
-            rst_buffer = io.Buffer("i", self._ports[reset.port_name])
+            domain = reset.iomodel['clock_domain']
+            rst_buffer = io.Buffer(io.Direction.Input, self._ports[reset.port_name])
             setattr(m.submodules, reset.port_name, rst_buffer)
             setattr(m.submodules, reset.port_name + "_sync", FFSynchronizer(rst_buffer.i, ResetSignal()))  #type: ignore[reportAttributeAccessIssue]
 

chipflow_lib/steps/silicon.py

@@ -173,13 +173,12 @@ def network_err(e):
                     fh.close()
                 exit(1)
 
-            sp.info(f"> Submitting {submission_name} for project {self.config.chipflow.project_name} to ChipFlow Cloud {self._chipflow_api_origin}")
+            sp.info(f"> Submitting {submission_name} for project {self.config.chipflow.project_name} to ChipFlow Cloud {build_submit_url}")
             sp.start("Sending design to ChipFlow Cloud")
 
-            build_submit_url = f"{self._chipflow_api_origin}/build/submit"
+            build_submit_url = f"{build_submit_url}/build/submit"
 
             assert self._chipflow_api_key
-            assert self._chipflow_api_origin
             try:
                 resp = requests.post(
                     build_submit_url,
@@ -210,9 +209,9 @@ def network_err(e):
             # Handle response based on status code
             if resp.status_code == 200:
                 logger.debug(f"Submitted design: {resp_data}")
-                self._build_url = f"{self._chipflow_api_origin}/build/{resp_data['build_id']}"
-                self._build_status_url = f"{self._chipflow_api_origin}/build/{resp_data['build_id']}/status"
-                self._log_stream_url = f"{self._chipflow_api_origin}/build/{resp_data['build_id']}/logs?follow=true"
+                self._build_url = f"{build_submit_url}/build/{resp_data['build_id']}"
+                self._build_status_url = f"{build_submit_url}/build/{resp_data['build_id']}/status"
+                self._log_stream_url = f"{build_submit_url}/build/{resp_data['build_id']}/logs?follow=true"
 
                 sp.succeed(f"✅ Design submitted successfully! Build URL: {self._build_url}")