Wire up the extra signals for sky130 io

Author: robtaylor

chipflow_lib/platforms/__init__.py

@@ -9,12 +9,13 @@
 from .silicon import SiliconPlatformPort, SiliconPlatform
 from .sim import SimPlatform
 from .utils import (
-        IO_ANNOTATION_SCHEMA, IOSignature, IOModel,
+        IO_ANNOTATION_SCHEMA, IOSignature, IOModel, IODriveMode, IOTripPoint, IOModelOptions,
         OutputIOSignature, InputIOSignature, BidirIOSignature,
         )
 from ._packages import PACKAGE_DEFINITIONS
 
-__all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature', 'IOModel',
+__all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature',
+           'IOModel', 'IOModelOptions', 'IODriveMode', 'IOTripPoint',
            'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
            'SiliconPlatformPort', 'SiliconPlatform',
            'SimPlatform',

chipflow_lib/platforms/silicon.py

@@ -1,5 +1,4 @@
 # amaranth: UnusedElaboratable=no
-# type: ignore[reportAttributeAccessIssue]
 
 # SPDX-License-Identifier: BSD-2-Clause
 import logging
@@ -8,6 +7,8 @@
 import subprocess
 
 from dataclasses import dataclass
+from pprint import pformat
+from typing import TYPE_CHECKING, List, Dict
 
 from amaranth import Module, Signal, Cat, ClockDomain, ClockSignal, ResetSignal
 
@@ -20,7 +21,10 @@
 from amaranth.hdl._ir import PortDirection
 
 from .. import ChipFlowError
-from .utils import load_pinlock, Port
+from .utils import load_pinlock, PortDesc, Pin, IOModel, IODriveMode, IOTripPoint, Process
+
+if TYPE_CHECKING:
+    from ..config_models import Config
 
 __all__ = ["SiliconPlatformPort", "SiliconPlatform"]
 
@@ -67,47 +71,67 @@ def elaborate(self, platform):
 
 class SiliconPlatformPort(io.PortLike):
     def __init__(self,
-                 component: str,
                  name: str,
-                 port: Port,
+                 port_desc: PortDesc,
                  *,
                  invert: bool = False):
-        self._direction = io.Direction(port.iomodel['direction'])
+        self._port_desc = port_desc
         self._invert = invert
-        self._iomodel = port.iomodel
-        self._pins = port.pins if port.pins else []
+        self._name = name
 
         # Initialize signal attributes to None
         self._i = None
         self._o = None
         self._oe = None
 
         # Create signals based on direction
-        if self._direction in (io.Direction.Input, io.Direction.Bidir):
-            self._i = Signal(port.width, name=f"{component}_{name}__i")
-        if self._direction in (io.Direction.Output, io.Direction.Bidir):
-            self._o = Signal(port.width, name=f"{component}_{name}__o")
-        if self._direction is io.Direction.Bidir:
-            if "individual_oe" in self._iomodel and self._iomodel["individual_oe"]:
-                self._oe = Signal(port.width, name=f"{component}_{name}__oe", init=-1)
+        if self.direction in (io.Direction.Input, io.Direction.Bidir):
+            self._i = Signal(self._port_desc.width, name=f"{self._name}__i")
+        if self.direction in (io.Direction.Output, io.Direction.Bidir):
+            self._o = Signal(self._port_desc.width, name=f"{self._name}__o")
+        if self.direction is io.Direction.Bidir:
+            if "individual_oe" in self.iomodel and self.iomodel["individual_oe"]:
+                self._oe = Signal(self._port_desc.width, name=f"{self._name}__oe", init=-1)
             else:
-                self._oe = Signal(1, name=f"{component}_{name}__oe", init=-1)
-        elif self._direction is io.Direction.Output:
+                self._oe = Signal(1, name=f"{self._name}__oe", init=-1)
+        elif self.direction is io.Direction.Output:
             # Always create an _oe for output ports
-            self._oe = Signal(1, name=f"{component}_{name}__oe", init=-1)
+            self._oe = Signal(1, name=f"{self._name}__oe", init=-1)
 
-        logger.debug(f"Created SiliconPlatformPort {name}, width={len(self._pins)},dir{self._direction}")
+        logger.debug(f"Created SiliconPlatformPort {self._name}, invert={invert} with port description:\n{pformat(self._port_desc)}")
 
     def wire(self, m: Module, interface: PureInterface):
-        assert self._direction == interface.signature.direction  #type: ignore
+        assert self.direction == interface.signature.direction  #type: ignore
         if hasattr(interface, 'i'):
             m.d.comb += interface.i.eq(self.i)  # type: ignore
         for d in ['o', 'oe']:
             if hasattr(interface, d):
                 m.d.comb += getattr(self, d).eq(getattr(interface, d))
 
+    def instantiate_toplevel(self):
+        ports = []
+        if self.direction in (io.Direction.Input, io.Direction.Bidir):
+            ports.append((f"io${self._name}$i", self.i, PortDirection.Input))
+        if self.direction in (io.Direction.Output, io.Direction.Bidir):
+            ports.append((f"io${self._name}$o", self.o, PortDirection.Output))
+        if self.direction is io.Direction.Bidir:
+            ports.append((f"io${self._name}$oe", self.oe, PortDirection.Output))
+        return ports
+
+    @property
+    def name(self) -> str:
+        return self._name
+
+    @property
+    def pins(self) -> List[Pin]:
+        return self._port_desc.pins if self._port_desc.pins else []
+
     @property
+    def iomodel(self) -> IOModel:
+        return self._port_desc.iomodel
 
+
+    @property
     def i(self):
         if self._i is None:
             raise AttributeError("SiliconPlatformPort with output direction does not have an "
@@ -130,69 +154,172 @@ def oe(self):
 
     @property
     def direction(self):
-        return self._direction
-
-    @property
-    def pins(self):
-        return self._pins
+        return self._port_desc.iomodel['direction']
 
     @property
     def invert(self):
         return self._invert
 
 
     def __len__(self):
-        if self._direction is io.Direction.Input:
+        if self.direction is io.Direction.Input:
             return len(self.i)
-        if self._direction is io.Direction.Output:
+        if self.direction is io.Direction.Output:
             return len(self.o)
-        if self._direction is io.Direction.Bidir:
+        if self.direction is io.Direction.Bidir:
             assert len(self.i) == len(self.o)
-            if 'individual_oe' in self._iomodel and self._iomodel["individual_oe"]:
+            if 'individual_oe' in self.iomodel and self.iomodel["individual_oe"]:
                 assert len(self.o) == len(self.oe)
             else:
                 assert len(self.oe) == 1
             return len(self.i)
         assert False  # :nocov:
 
     def __getitem__(self, key):
-        result = object.__new__(type(self))
-        result._i = None if self._i is None else self._i[key]
-        result._o = None if self._o is None else self._o[key]
-        result._oe = None if self._oe is None else self._oe[key]
-        result._invert = self._invert
-        result._direction = self._direction
-        result._iomodel = self._iomodel
-        result._pins = self._pins
-        return result
+        return NotImplemented
 
     def __invert__(self):
-        result = object.__new__(type(self))
-        result._i = self._i
-        result._o = self._o
-        result._oe = self._oe
-        result._invert = not self._invert
-        result._direction = self._direction
-        result._iomodel = self._iomodel
-        result._pins = self._pins
+        result = SiliconPlatformPort(self._name, self._port_desc, invert=not self.invert)
         return result
 
     def __add__(self, other):
-        direction = self._direction & other._direction
-        result = object.__new__(type(self))
-        result._i = None if direction is io.Direction.Output else Cat(self._i, other._i)
-        result._o = None if direction is io.Direction.Input else Cat(self._o, other._o)
-        result._oe = None if direction is io.Direction.Input else Cat(self._oe, other._oe)
-        result._invert = self._invert
-        result._direction = direction
-        result._iomodel = self._iomodel
-        result._pins = self._pins + other._pins
+        return NotImplemented
+
+    def __repr__(self):
+        return (f"SiliconPlatformPort(name={self._name}, invert={self._invert}, iomode={self.iomodel})")
+
+
+class Sky130Port(SiliconPlatformPort):
+    """
+    Specialisation of `SiliconPlatformPort` for the `Skywater sky130_fd_io__gpiov2 IO cell <https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_io/docs/user_guide.html>`_
+
+    Includes wires and configuration for `Drive Modes <IODriveMode>`, `Input buffer trip point <IOTripPoint>`and buffer control~
+    """
+
+    _DriveMode_map = {
+        # Strong pull-up, weak pull-down
+        IODriveMode.STRONG_UP_WEAK_DOWN: 0b011,
+        # Weak pull-up, Strong pull-down
+        IODriveMode.WEAK_UP_STRONG_DOWN: 0b010,
+        # Open drain with strong pull-down
+        IODriveMode.OPEN_DRAIN_STRONG_DOWN: 0b100,
+        # Open drain-with strong pull-up
+        IODriveMode.OPEN_DRAIN_STRONG_UP: 0b101,
+        # Strong pull-up, weak pull-down
+        IODriveMode.STRONG_UP_STRONG_DOWN: 0b110,
+        # Weak pull-up, weak pull-down
+        IODriveMode.WEAK_UP_WEAK_DOWN: 0b111
+    }
+
+    _VTrip_map = {
+        # CMOS level switching (30%/70%) referenced to IO power domain
+        IOTripPoint.CMOS: (0, 0),
+        # TTL level switching (low < 0.8v, high > 2.0v) referenced to IO power domain
+        IOTripPoint.TTL: (0, 1),
+        # CMOS level switching referenced to core power domain (e.g. low power mode)
+        IOTripPoint.VCORE: (1,0),
+        # CMOS level switching referenced to external reference voltage (e.g. low power mode)
+        # Only available on sky130_fd_io__gpio_ovtv2
+        # VREF
+    }
+
+
+    # TODO: slew rate, hold points
+    def __init__(self,
+                 name: str,
+                 port_desc: PortDesc,
+                 *,
+                 invert: bool = False):
+        super().__init__(name, port_desc, invert=invert)
+
+        # keep a list of signals we create
+        self._signals = []
+
+        # Now create the signals for ``gpio_oeb`` (``oe_n``), ``gpio_inp_dis`` (``ie``)
+        self._oe_n = None
+        self._ie = None
+
+        if self._oe is not None:
+            self._oe_n = Signal(self._oe.width, name=f"{self._name}$oeb")
+            self._signals.append((self._oe_n, PortDirection.Output))
+        if self._i is not None:
+            self._ie = Signal(self._i.width, name=f"{self._name}$inp_dis")
+            self._signals.append((self._ie, PortDirection.Input))
+
+        # Port Configuration
+        # Input voltage trip level
+        if self.direction in (io.Direction.Input, io.Direction.Bidir):
+            if 'trip_point' in port_desc.iomodel:
+                trip_point = port_desc.iomodel['trip_point']
+                if trip_point not in __class__._VTrip_map:
+                    raise ChipFlowError(f"Trip point `{trip_point}` not available for {__class__.__name__}")
+                ib_mode_init, vtrip_init = __class__._VTrip_map[trip_point]
+            else:
+                ib_mode_init = vtrip_init = 0
+
+            self._gpio_ib_mode_sel =  Signal(1, name=f"{self._name}$ib_mode_sel", init=ib_mode_init)
+            self._signals.append((self._gpio_ib_mode_sel, PortDirection.Output))
+            self._gpio_vtrip_sel = Signal(1, name=f"{self._name}$vtrip_sel", init=vtrip_init)
+            self._signals.append((self._gpio_vtrip_sel, PortDirection.Output))
+
+        # Drive mode
+        if self.direction in (io.Direction.Output, io.Direction.Bidir):
+            if 'drive_mode' in port_desc.iomodel:
+                dm = port_desc.iomodel['drive_mode']
+            else:
+                dm = IODriveMode.STRONG_UP_STRONG_DOWN
+            dm_init = __class__._DriveMode_map[dm]
+            self._gpio_dm = Signal(3, name=f"{self._name}$dm", init=dm_init)
+            self._signals.append((self._gpio_dm, PortDirection.Output))
+
+        # Not enabled yet:
+        self._gpio_slow_sel = None  # Select slew rate
+        self._gpio_holdover = None  # Hold mode
+        # Analog config, not enabled yet
+        # see https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_io/docs/user_guide.html#analog-functionality
+        self._gpio_analog_en = None # analog enable
+        self._gpio_analog_sel = None # analog mux select
+        self._gpio_analog_pol = None # analog mux select
+
+    def wire(self, m: Module, interface: PureInterface):
+        super().wire(m, interface)
+        # don't wire up oe_n
+        if hasattr(interface, 'ie'):
+            m.d.comb += interface.ie.eq(self._ie)  # type: ignore
+        # wire up oe_n = ~oe
+        if self._oe is not None:
+            assert self._oe_n is not None
+            m.d.comb += self._oe_n.eq(~self._oe)
+
+    def instantiate_toplevel(self):
+        ports = super().instantiate_toplevel()
+        for s, d in self._signals:
+            print(f"appending io${s.name}")
+            ports.append((f"io${s.name}", s, d))
+        return ports
+
+    @property
+    def ie(self):
+        if self._ie is None:
+            raise AttributeError("SiliconPlatformPort with input direction does not have an "
+                                 "input enable signal")
+        return self._ie
+
+    def __invert__(self):
+        result = Sky130Port(self._name, self._port_desc, invert=not self.invert)
         return result
 
     def __repr__(self):
-        return (f"SiliconPlatformPort(direction={repr(self._direction)}, width={len(self)}, "
-                f"i={repr(self._i)}, o={repr(self._o)}, oe={repr(self._oe)}, "
-                f"invert={repr(self._invert)})")
+        return (f"Sky130Port(name={self._name}, invert={self._invert}, iomode={self.iomodel})")
+
+
+
+def port_for_process(p: Process):
+    match p:
+        case Process.SKY130:
+            return Sky130Port
+        case Process.GF180 | Process.HELVELLYN2 | Process.GF130BCD | Process.IHP_SG13G2:
+            return SiliconPlatformPort
 
 
 class IOBuffer(io.Buffer):
@@ -258,7 +385,9 @@ def elaborate(self, platform):
 
 
 class SiliconPlatform:
-    def __init__(self, config):
+    def __init__(self, config: 'Config'):
+        if not config.chipflow.silicon:
+            raise ChipFlowError(f"I can't build for silicon without a [chipflow.silicon] section to guide me!")
         self._config = config
         self._ports = {}
         self._files = {}
@@ -269,24 +398,28 @@ def ports(self):
         return self._ports
 
     def instantiate_ports(self, m: Module):
+        assert self._config.chipflow.silicon
         if hasattr(self, "pinlock"):
             return
 
         pinlock = load_pinlock()
         for component, iface in pinlock.port_map.ports.items():
-            for k, v in iface.items():
+            for interface, v in iface.items():
                 for name, port in v.items():
-                    self._ports[port.port_name] = SiliconPlatformPort(component, name, port)
+                    self._ports[port.port_name] = port_for_process(self._config.chipflow.silicon.process)(port.port_name, port)
 
+        print(pformat(self._ports))
         for clock in pinlock.port_map.get_clocks():
+            assert 'clock_domain' in clock.iomodel
             domain = name=clock.iomodel['clock_domain']
             setattr(m.domains, domain, ClockDomain(name=domain))
             clk_buffer = io.Buffer("i", self._ports[clock.port_name])
             setattr(m.submodules, "clk_buffer_" + domain, clk_buffer)
             m.d.comb += ClockSignal().eq(clk_buffer.i)  #type: ignore[reportAttributeAccessIssue]
 
         for reset in pinlock.port_map.get_resets():
-            domain = name=clock.iomodel['clock_domain']
+            assert 'clock_domain' in reset.iomodel
+            domain = name=reset.iomodel['clock_domain']
             rst_buffer = io.Buffer("i", self._ports[reset.port_name])
             setattr(m.submodules, reset.port_name, rst_buffer)
             setattr(m.submodules, reset.port_name + "_sync", FFSynchronizer(rst_buffer.i, ResetSignal()))  #type: ignore[reportAttributeAccessIssue]
@@ -343,13 +476,8 @@ def _prepare(self, elaboratable, name="top"):
 
         # Prepare toplevel ports according to pinlock
         ports = []
-        for port_name, port in self._ports.items():
-            if port.direction in (io.Direction.Input, io.Direction.Bidir):
-                ports.append((f"io${port_name}$i", port.i, PortDirection.Input))
-            if port.direction in (io.Direction.Output, io.Direction.Bidir):
-                ports.append((f"io${port_name}$o", port.o, PortDirection.Output))
-            if port.direction is io.Direction.Bidir:
-                ports.append((f"io${port_name}$oe", port.oe, PortDirection.Output))
+        for port in self._ports.values():
+            ports.extend(port.instantiate_toplevel())
 
         # Prepare design for RTLIL conversion.
         return fragment.prepare(ports)