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Updated documnetation for all sections of the chipflow.toml
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docs/chipflow-toml-guide.rst

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@@ -28,13 +28,33 @@ Let's start with a typical example:
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The ``project_name`` is a human-readable identifier for this project. If not set, the tool and library will use the project name configured in ``pyproject.toml``.
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``[chipflow.top]``
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------------------
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.. code-block:: TOML
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[chipflow.top]
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soc = "my_design.design:MySoC"
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This section outlines the design modules that need to be instantiated.
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A new top module will be automatically generated, incorporating all specified modules along with their interfaces.
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Each entry follows the format `<instance name> = <module class path>`.
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The instance name is the name the python object will be given in your design, and the :term:`module class path`
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.. glossary::
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module class path
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The module class path offers a way to locate Python objects as entry points.
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It consists of a module's :term:`qualified name` followed by a colon (:) and then the :term:`qualified name` of the class within that module.
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``[chipflow.steps]``
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--------------------
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The ``steps`` section allows overriding or addition to the standard steps available from `chipflow_lib`_.
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The ``steps`` section allows overriding or addition to the standard steps available from `chipflow_lib`.
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For example, if you want to override the standard silicon preparation step, you could derive from :class:`chipflow_lib.steps.silicon.SiliconStep`, add your custom functionality
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and add the following to your `chipflow.toml`, with the appropriate Python `qualified name`_ :
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and add the following to your `chipflow.toml`, with the appropriate :term:`module class path`:
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.. code-block:: TOML
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@@ -44,8 +64,7 @@ and add the following to your `chipflow.toml`, with the appropriate Python `qual
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You probably won't need to change these if you're starting from an example repository.
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.. _chipflow_lib: https://github.com/ChipFlow/chipflow-lib]
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.. _qualified name: https://docs.python.org/3/glossary.html#term-qualified-name
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.. _chipflow_lib: https://github.com/ChipFlow/chipflow-lib
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``[chipflow.clocks]``
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default = 'sys_clk'
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This section links the clock domains utilized in the design to specific pads.
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These pads need to be specified in the `[silicon.pads]`_ section with `type`_ equal to ``clock``.
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The ``default`` clock domain is associated with the Amaranth ``sync`` clock domain.
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These pads need to be specified in the `[silicon.pads]`_ section with the :term:type set to :term:clock.
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The ``default`` clock domain is associated with the Amaranth :any:`sync <lang-domains>` :ref:`clock domain <lang-clockdomains>`.
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Currently, only one ``default`` clock domain is supported.
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default = 'sys_rst_n'
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This section identifies the input pads designated for reset functionality.
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These pads need to be specified in the `[silicon.pads]`_ section with `type`_ equal to ``reset``.
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These pads need to be specified in the `[silicon.pads]`_ section with the :term:type set to :term:reset.
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The logic that synchronizes the reset signal with the clock will be generated automatically.
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``[chipflow.silicon]``
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+------------+------------+---------------------------+
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Available pad rings
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---------------------------------
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-------------------
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+----------+-----------+--------------------+------------------------------------+
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| Pad ring | Pad count | Pad locations | Notes |
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+----------+-----------+--------------------+------------------------------------+
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_`[silicon.pads]`
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==================
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``[silicon.pads]``
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------------------
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The ``silicon.pads`` section lists special pads. In general you are unlikely to need to add to this.
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Each pad specified with the name used by the design and two parameters: `type`_ and `loc`_.
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Each pad specified with the name used by the design and two parameters: :term:type and :term:`loc`.
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.. code-block:: TOML
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In the above example two pads specified, ``sys_clk`` pad for clock input and ``sys_rst_n`` for reset.
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_`type`
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-------
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The ``type`` for each pad can be set to one of:
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clock
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External clock input.
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reset
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External reset input.
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.. glossary::
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i
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Input.
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loc
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This is the physical location of the pad on your chosen pad ring. How these are indexed varies by the pad ring.
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o
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Output.
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type
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The :term:type for each pad can be set to one of :term:clock or :term:reset.
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io
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Both input and output.
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clock
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External clock input.
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_`loc`
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------
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reset
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External reset input.
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This is the physical location of the pad on your chosen pad ring. How these are indexed varies by the pad ring.
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silicon.power
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=============
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``[silicon.power]``
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-------------------
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This section describes how the pads should be connected to the power available on the chosen process and package.
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This section outlines the connection of pads to the power supply available for the selected process and package.
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These pads are declared with the :term:type and :term:loc parameters, similar to the `[silicon.pads]`_ section.
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Note that in this context, the :term:type parameter can only be ``ground`` or ``power``.
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This is a work in progress, and currently you can use the defaults provided by customer support.
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.. _Caravel Harness: https://caravel-harness.readthedocs.io/en/latest/
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docs/conf.py

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# Napoleon settings
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napoleon_google_docstring = True
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napoleon_numpy_docstring = True
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napoleon_use_ivar = True
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napoleon_include_init_with_doc = True
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napoleon_include_private_with_doc = True
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napoleon_include_special_with_doc = True
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napoleon_use_admonition_for_examples = False
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napoleon_use_admonition_for_notes = False
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napoleon_use_admonition_for_references = False
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napoleon_use_ivar = False
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napoleon_use_param = True
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napoleon_use_rtype = True
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napoleon_custom_sections = [
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("Arguments", "params_style"), # by default displays as "Parameters"
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("Attributes", "params_style"), # by default displays as "Variables", which is confusing
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("Members", "params_style"), # `amaranth.lib.wiring` signature members
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]
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rst_prolog = """
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.. role:: py(code)

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