- Implement a single bit pdm. Include an integration test (#20)

- Use output pins without pins interface

- pdm outval can now be maximum 16 bits
- modify header to replace din with outval

- add unit test for pdm

Author: saif-chipflow

my_design/design.py

@@ -20,6 +20,7 @@
 from .ips.spi import SPISignature, SPIPeripheral
 from .ips.i2c import I2CSignature, I2CPeripheral
 from .ips.pwm import PWMPins, PWMPeripheral
+from .ips.pdm import PDMPeripheral
 
 __all__ = ["JTAGSignature", "MySoC"]
 
@@ -45,7 +46,7 @@ def __init__(self):
         self.user_spi_count = 3
         self.i2c_count = 2
         self.motor_count = 10
-        self.pdm_ao_width = 6
+        self.pdm_ao_count = 6
         self.uart_count = 2
 
         self.gpio_banks = 2
@@ -60,7 +61,8 @@ def __init__(self):
         for i in range(self.motor_count):
             interfaces[f"motor_pwm{i}"] = Out(PWMPins.Signature())
 
-        interfaces[f"pdm_ao"] = Out(self.pdm_ao_width)
+        for i in range(self.pdm_ao_count):
+            interfaces[f"pdm_ao_{i}"] = Out(1)
 
         for i in range(self.uart_count):
             interfaces[f"uart_{i}"] = Out(UARTPins.Signature())
@@ -90,8 +92,9 @@ def __init__(self):
         self.csr_motor_base    = 0xb7000000
         self.csr_pdm_ao_base   = 0xb8000000
 
-        self.periph_offset    = 0x00100000
-        self.motor_offset     = 0x00000100
+        self.periph_offset     = 0x00100000
+        self.motor_offset      = 0x00000100
+        self.pdm_ao_offset     = 0x00000010
 
         self.sram_size  = 0x800 # 2KiB
         self.bios_start = 0x100000 # 1MiB into spiflash to make room for a bitstream
@@ -213,18 +216,15 @@ def elaborate(self, platform):
             sw.add_periph("motor_pwm", f"MOTOR_PWM{i}", base_addr)
             setattr(m.submodules, f"motor_pwm{i}", motor_pwm)
 
-        # PDM for analog outputs
-        # TODO: create a PDM peripheral and replace this GPIO
-        soft_pdm_pins = GPIOPins(width=self.pdm_ao_width)
-        pdm = GPIOPeripheral(name=f"pdm_ao", pins=soft_pdm_pins)
-
-        csr_decoder.add(pdm.bus, addr=self.csr_pdm_ao_base - self.csr_base)
-        sw.add_periph("gpio", f"PDM_AO_{i}", self.csr_pdm_ao_base)
-
-        # FIXME: This assignment will disappear once we have a relevant peripheral available
-        m.d.comb += [self.pdm_ao.eq(soft_pdm_pins.o)]
-
-        m.submodules.pdm_ao = pdm
+        # pdm_ao
+        for i in range(self.pdm_ao_count):
+            pdm = PDMPeripheral(name=f"pdm{i}", bitwidth=10)
+            base_addr = self.csr_pdm_ao_base + i * self.pdm_ao_offset
+            csr_decoder.add(pdm.bus, addr=base_addr  - self.csr_base)
+        
+            sw.add_periph("pdm", f"PDM{i}", base_addr)
+            setattr(m.submodules, f"pdm{i}", pdm)          
+            m.d.comb += getattr(self, f"pdm_ao_{i}").eq(pdm.pdm_ao)
 
         # SoC ID
 

my_design/ips/pdm.py

@@ -0,0 +1,71 @@
+
+from amaranth import *
+from amaranth import Elaboratable, Module
+from amaranth.build import Platform
+
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out, flipped, connect
+from amaranth_soc import csr
+
+__all__ = ["PDMPeripheral"]
+     
+class PDMPeripheral(wiring.Component):
+    class OutVal(csr.Register, access="rw"):
+        """Analog sample value"""
+        val: csr.Field(csr.action.RW, unsigned(16))
+
+    class Conf(csr.Register, access="rw"):
+        """Configuration register """
+        en: csr.Field(csr.action.RW, unsigned(1))
+
+
+    def __init__(self, *, name, bitwidth):
+        self._bitwidth = bitwidth
+
+
+        regs = csr.Builder(addr_width=3, data_width=8, name=name)
+
+        self._outval = regs.add("outval", self.OutVal(), offset=0x0)
+        self._conf = regs.add("conf", self.Conf(), offset=0x4)
+
+        self._bridge = csr.Bridge(regs.as_memory_map())
+
+        super().__init__({
+            "bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
+            "pdm_ao": Out(1),
+        })
+        self.bus.memory_map = self._bridge.bus.memory_map
+
+    @property
+    def bitwidth(self):
+        return self._bitwidth
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.bridge = self._bridge
+        maxval = Const(int((2**self._bitwidth)-1), unsigned(self._bitwidth))        
+        error = Signal(unsigned(self._bitwidth), reset=0x0)
+        error_0 = Signal(unsigned(self._bitwidth), reset=0x0)
+        error_1 = Signal(unsigned(self._bitwidth), reset=0x0)
+        pdm_ao = Signal()
+        connect(m, flipped(self.bus), self._bridge.bus)
+        m.d.sync += [
+            error_1.eq(error + maxval - self._outval.f.val.data),
+            error_0.eq(error - self._outval.f.val.data),
+        ]
+        with m.If(self._outval.f.val.data >= error):
+            m.d.sync += [ 
+                pdm_ao.eq(1),
+                error.eq(error_1),
+            ]
+        with m.Else():
+            m.d.sync += [ 
+                pdm_ao.eq(0),
+                error.eq(error_0),
+            ]
+
+        with m.If(self._conf.f.en.data == 1):
+            m.d.comb += self.pdm_ao.eq(pdm_ao)
+        with m.Else():
+            m.d.comb += self.pdm_ao.eq(0)            
+        return m

my_design/ips/test_pdm.py

@@ -0,0 +1,74 @@
+from amaranth import *
+from amaranth.sim import Simulator, Tick
+
+from pdm import PDMPeripheral
+import unittest
+
+class TestPdmPeripheral(unittest.TestCase):
+
+    REG_OUTVAL = 0x00
+    REG_CONF = 0x04
+
+
+    def _write_reg(self, dut, reg, value, width=4):
+        for i in range(width):
+            yield dut.bus.addr.eq(reg + i)
+            yield dut.bus.w_data.eq((value >> (8 * i)) & 0xFF)
+            yield dut.bus.w_stb.eq(1)
+            yield Tick()
+        yield dut.bus.w_stb.eq(0)
+
+    def _check_reg(self, dut, reg, value, width=4):
+        result = 0
+        for i in range(width):
+            yield dut.bus.addr.eq(reg + i)
+            yield dut.bus.r_stb.eq(1)
+            yield Tick()
+            result |= (yield dut.bus.r_data) << (8 * i)
+        yield dut.bus.r_stb.eq(0)
+        self.assertEqual(result, value)
+
+    def test_pdm_ao(self):
+        dut = PDMPeripheral(name="dut", bitwidth=10)
+        def testbench():
+            yield from self._write_reg(dut, self.REG_OUTVAL, 0xFF, 4)
+            yield Tick()
+            yield from self._write_reg(dut, self.REG_CONF, 0x1, 1)
+            for i in range(6): yield Tick()
+            self.assertEqual((yield dut.pdm_ao), 1) # assert two cycles of logic '1' (4us)
+            yield Tick()
+            self.assertEqual((yield dut.pdm_ao), 1)
+            yield Tick()
+            self.assertEqual((yield dut.pdm_ao), 0) # assert 6 cycles of logic '0' (12us)
+            for i in range(5): yield Tick()
+            self.assertEqual((yield dut.pdm_ao), 0)
+            yield Tick()
+            self.assertEqual((yield dut.pdm_ao), 1) # assert start of the next pulse
+            for i in range(50): yield Tick()
+        sim = Simulator(dut)
+        sim.add_clock(2e-6)
+        sim.add_testbench(testbench)
+        with sim.write_vcd("pdm_ao_test.vcd", "pdm_ao_test.gtkw"):
+            sim.run()
+
+    def test_conf(self):
+        dut = PDMPeripheral(name="dut", bitwidth=10)
+        def testbench():
+            yield from self._write_reg(dut, self.REG_OUTVAL, 0xFF, 4)
+            yield Tick()
+            yield from self._write_reg(dut, self.REG_CONF, 0x1, 1)
+            for i in range(6): yield Tick()
+            self.assertEqual((yield dut.pdm_ao), 1)
+            yield from self._write_reg(dut, self.REG_CONF, 0x0, 1)
+            yield Tick()
+            self.assertEqual((yield dut.pdm_ao), 0)
+            for i in range(50): yield Tick()
+        sim = Simulator(dut)
+        sim.add_clock(2e-6)
+        sim.add_testbench(testbench)
+        with sim.write_vcd("pdm_conf_test.vcd", "pdm_conf_test.gtkw"):
+            sim.run()
+
+if __name__ == "__main__":
+    unittest.main()
+

my_design/software/drivers/pdm.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+#ifndef PDM_H
+#define PDM_H
+
+#include <stdint.h>
+
+typedef struct {
+    uint32_t outval;
+    uint32_t conf;
+} pdm_regs_t;
+
+#endif
+

my_design/software/main.c

@@ -82,7 +82,15 @@ void main() {
     MOTOR_PWM9->numr = 0x7F;
     MOTOR_PWM9->denom = 0xFF;
     MOTOR_PWM9->conf = 0x3;
-
+	
+    PDM0->outval = 0xFF;
+    PDM1->outval = 0x7F;
+    PDM2->outval = 0x3F;
+
+    PDM0->conf = 0x1;
+    PDM1->conf = 0x1;
+    PDM2->conf = 0x0;
+	
     puts("GPIO: ");
     puthex(GPIO_1->in);
     puts(" ");

my_design/steps/_chipflow_top.py

@@ -52,7 +52,7 @@ def _connect_interface(interface, name):
             _connect_interface(getattr(soc, f"motor_pwm{pwm_idx}"), f"motor_pwm{pwm_idx}")
 
         for ao_idx in range(6):
-            m.d.comb += platform.request(f"pdm_ao_{ao_idx}").o.eq(soc.pdm_ao[ao_idx])
+            m.d.comb += platform.request(f"pdm_ao_{ao_idx}").o.eq(getattr(soc, f"pdm_ao_{ao_idx}"))
 
         for gpio_bank in range(2):
             gpio = getattr(soc, f"gpio_{gpio_bank}")