Fix of generation verilog modules

Author: johnymil-chipflow

Makefile

@@ -32,9 +32,13 @@ sim-run: sim-build software-build
 sim-check: sim-run
 	pdm run python -m my_design.tools.json_compare my_design/tests/events_reference.json build/sim/events.json
 
+.PHONY: pyuvm-gen-verilog
+pyuvm-gen-verilog: init
+	pdm run python -m my_design.ips.spi
+
 .PHONY: verif-run-pyuvm
-verif-run-pyuvm: init
-	YOSYS=yowasp-yosys pdm run chipflow export --dir pyuvm_verif/verilog
+verif-run-pyuvm: pyuvm-gen-verilog
+	AMARANTH_USE_YOSYS=builtin pdm run chipflow export --dir pyuvm_verif/verilog
 	pdm run make -C pyuvm_verif -j4 ARG=$(ARG)
 
 .PHONY: silicon-prepare # Build RTLIL for the design

pdm.lock

@@ -13,8 +13,9 @@ license = {file = "LICENSE.md"}
 
 requires-python = "~=3.9"
 dependencies = [
-  "chipflow-lib @ git+https://github.com/ChipFlow/chipflow-lib.git@main",
+  "amaranth[builtin-yosys] @ git+https://github.com/amaranth-lang/amaranth",
   "amaranth-cv32e40p @ git+https://github.com/ChipFlow/amaranth-cv32e40p@main",
+  "chipflow-lib @ git+https://github.com/ChipFlow/chipflow-lib.git@main",
   "pyuvm~=2.9.1",
   "ziglang==0.11.0",
 ]

pyproject.toml

@@ -1,6 +1,6 @@
 CWD=$(shell pwd)
 SIM=verilator
-VERILOG_SOURCES=$(wildcard $(CWD)/*/*.v)
+VERILOG_SOURCES=$(wildcard $(CWD)/verilog/*.v) $(wildcard $(CWD)/../build/export/ips/*.v)
 .PHONY: print_vars
 
 ifeq ($(ARG),SPI)