wip: now somehat generating flash load

Author: robtaylor

chipflow_lib/common/sim/main.cc.jinja

@@ -52,7 +52,10 @@ int main(int argc, char **argv) {
         //     agent.breakpoint(CXXRTL_LOCATION);
     };
 
-    flash.load_data(BUILD_DIR "/software/software.bin", 0x00100000U);
+    {% for data in data_load %}
+    {{data.model_name}}.load_data("{{data.file_name}}", {{data.args | join(', ')}});
+    {% endfor %}
+
     agent.step();
     agent.advance(1_us);
 

chipflow_lib/common/sim/models.h

@@ -103,7 +103,7 @@ struct gpio_model {
 
 struct spi_model {
     std::string name;
-    spi_model(const std::string &name, const value<1> &clk, const value<1> &csn, const value<1> &copi, value<1> &cipo) : 
+    spi_model(const std::string &name, const value<1> &clk, const value<1> &copi, value<1> &cipo, const value<1> &csn) : 
         name(name), clk(clk), csn(csn), copi(copi), cipo(cipo) {
     };
 
@@ -127,7 +127,7 @@ struct spi_model {
 
 struct i2c_model {
     std::string name;
-    i2c_model(const std::string &name, const value<1> &sda_o, const value<1> &sda_oe, value<1> &sda_i, const value<1> &scl_o, const value<1> &scl_oe, value<1> &scl_i) : name(name), sda_oe(sda_oe), sda_i(sda_i), scl_oe(scl_oe), scl_i(scl_i) {};
+    i2c_model(const std::string &name, const value<1> &scl_o, const value<1> &scl_oe, value<1> &scl_i, const value<1> &sda_o, const value<1> &sda_oe, value<1> &sda_i)  : name(name), sda_oe(sda_oe), sda_i(sda_i), scl_oe(scl_oe), scl_i(scl_i) {};
 
     void step(unsigned timestamp);
 private:

chipflow_lib/platforms/_signatures.py

@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
+import re
 from typing_extensions import Unpack, TypedDict
 
 from amaranth.lib import wiring
@@ -10,38 +11,34 @@
 SIM_ANNOTATION_SCHEMA = str(_chipflow_schema_uri("sim-interface", 0))
 
 class SimInterface(TypedDict):
-    name: str
+    uid: str
     parameters: dict
 
+_VALID_UID = re.compile('[a-zA-Z_.]').search
 
-def sim_annotate(klass):
-    original_init_subclass = klass.__init_subclass__
+def sim_annotate(base="com.chipflow.chipflow_lib"):
+    def decorate(klass):
+        assert _VALID_UID(base)
+        dec = amaranth_annotate(SimInterface, SIM_ANNOTATION_SCHEMA)
+        klass = dec(klass)
 
-    def new_init_subclass(cls, /, **kwargs):
-        original_init = cls.__init__
+        original_init = klass.__init__
         def new_init(self,*args, **kwargs):
             original_init(self, *args, **kwargs)
-            self._model = {
-                 "name": cls.__name__,
-                 "parameters": self._get_sim_parameters(),
-                 }
+            self.__chipflow_annotation__ = {
+                "uid": klass.__chipflow_uid__,
+                "parameters": self.__chipflow_parameters__(),
+                }
 
-        if original_init_subclass:
-            original_init_subclass(**kwargs)
-        cls.__init__ = new_init
+        klass.__init__ = new_init
+        klass.__chipflow_uid__ = f"{base}.{klass.__name__}"
+        klass.__chipflow_parameters__ = lambda self: {}
+        return klass
+    return decorate
 
-    dec = amaranth_annotate(SimInterface, SIM_ANNOTATION_SCHEMA)
-    klass = dec(klass)
-    klass.__init_subclass__ = classmethod(new_init_subclass)
-    klass._get_sim_parameters = lambda self: {}
-    return klass
 
-
-@sim_annotate
-class SimulatableSignature(wiring.Signature):
-    ...
-
-class JTAGSignature(SimulatableSignature):
+@sim_annotate()
+class JTAGSignature(wiring.Signature):
     def __init__(self, **kwargs: Unpack[IOModelOptions]):
         super().__init__({
         "trst": Out(InputIOSignature(1)),
@@ -52,7 +49,8 @@ def __init__(self, **kwargs: Unpack[IOModelOptions]):
     })
 
 
-class SPISignature(SimulatableSignature):
+@sim_annotate()
+class SPISignature(wiring.Signature):
     def __init__(self, **kwargs: Unpack[IOModelOptions]):
         super().__init__({
             "sck": Out(OutputIOSignature(1)),
@@ -61,29 +59,34 @@ def __init__(self, **kwargs: Unpack[IOModelOptions]):
             "csn": Out(OutputIOSignature(1)),
         })
 
-class QSPIFlashSignature(SimulatableSignature):
+@sim_annotate()
+class QSPIFlashSignature(wiring.Signature):
     def __init__(self, **kwargs: Unpack[IOModelOptions]):
         super().__init__({
             "clk": Out(OutputIOSignature(1)),
             "csn": Out(OutputIOSignature(1)),
             "d": Out(BidirIOSignature(4, individual_oe=True)),
         })
 
-class UARTSignature(SimulatableSignature):
+@sim_annotate()
+class UARTSignature(wiring.Signature):
     def __init__(self, **kwargs: Unpack[IOModelOptions]):
         super().__init__({
             "tx": Out(OutputIOSignature(1)),
             "rx": Out(InputIOSignature(1)),
         })
 
-class I2CSignature(SimulatableSignature):
+@sim_annotate()
+class I2CSignature(wiring.Signature):
     def __init__(self, **kwargs: Unpack[IOModelOptions]):
         super().__init__({
         "scl": Out(BidirIOSignature(1)),
         "sda": Out(BidirIOSignature(1))
     })
 
-class GPIOSignature(SimulatableSignature):
+@sim_annotate()
+class GPIOSignature(wiring.Signature):
+
     def __init__(self, pin_count=1, **kwargs: Unpack[IOModelOptions]):
         if pin_count > 32:
             raise ValueError(f"Pin pin_count must be lesser than or equal to 32, not {pin_count}")
@@ -92,7 +95,8 @@ def __init__(self, pin_count=1, **kwargs: Unpack[IOModelOptions]):
         super().__init__({
             "gpio": Out(BidirIOSignature(pin_count, **kwargs))
             })
-    def _get_sim_parameters(self):
+
+    def __chipflow_parameters__(self):
         return {'pin_count': self._pin_count}
 
     def __repr__(self) -> str:

chipflow_lib/platforms/_utils.py

@@ -147,18 +147,18 @@ class Annotation(meta.Annotation):
         schema = annotation_schema()
 
         def __init__(self, model: modeltype):
-            self._model = model
+            self.__chipflow_annotation__ = model
 
         @property
         def origin(self):  # type: ignore
-            return self._model
+            return self.__chipflow_annotation__
 
         def as_json(self):  # type: ignore
-            return PydanticModel.dump_python(self._model)
+            return PydanticModel.dump_python(self.__chipflow_annotation__)
 
     def annotations(self, *args):  # type: ignore
         annotations = wiring.Signature.annotations(self, *args)  # type: ignore
-        annotation = Annotation(self._model)
+        annotation = Annotation(self.__chipflow_annotation__)
         return annotations + (annotation,)  # type: ignore
 
     def decorator(klass):
@@ -211,34 +211,35 @@ def __init__(self, **kwargs: Unpack[IOModel]):
         if 'clock_domain' not in model:
             model['clock_domain'] = 'sync'
 
-        self._model = model
+        self.__chipflow_annotation__ = model
         super().__init__(sig)
 
     @property
     def direction(self) -> io.Direction:
         "The direction of the IO port"
-        return self._model['direction']
+        return self.__chipflow_annotation__['direction']
 
     @property
     def width(self) -> int:
         "The width of the IO port, in wires"
-        return self._model['width']
+        return self.__chipflow_annotation__['width']
 
     @property
     def invert(self) -> Iterable[bool]:
         "A tuple as wide as the IO port, with a bool for the polarity inversion for each wire"
-        assert type(self._model['invert']) is tuple
-        return self._model['invert']
+        assert type(self.__chipflow_annotation__['invert']) is tuple
+        return self.__chipflow_annotation__['invert']
 
     @property
     def options(self) -> IOModelOptions:
         """
         Options set on the io port at construction
         """
-        return self._model
+        return self.__chipflow_annotation__
 
     def __repr__(self):
-        return f"IOSignature({','.join('{0}={1!r}'.format(k,v) for k,v in self._model.items())})"
+        return f"IOSignature({','.join('{0}={1!r}'.format(k,v) for k,v in self.__chipflow_annotation__.items())})"
+
 
 def OutputIOSignature(width: int, **kwargs: Unpack[IOModelOptions]):
     """This creates an :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` which is then used to decorate package output signals

chipflow_lib/platforms/sim.py

@@ -20,10 +20,10 @@
 from jinja2 import Environment, PackageLoader, select_autoescape
 from pydantic import BaseModel
 
-from .. import ChipFlowError
+from .. import ChipFlowError, _ensure_chipflow_root
 from ._signatures import (
         I2CSignature, GPIOSignature, UARTSignature, SPISignature, QSPIFlashSignature,
-        SimulatableSignature, SIM_ANNOTATION_SCHEMA, SimInterface
+        SIM_ANNOTATION_SCHEMA, SimInterface
         )
 from ._utils import load_pinlock, Interface
 
@@ -46,12 +46,15 @@ class SimModel:
         capabilities: List of capabilities of the model.
     """
     name: str
-    signature: Type[SimulatableSignature]
+    signature: Type[wiring.Signature]
     capabilities: Optional[List[SimModelCapability]] = None
 
+    def __post_init__(self):
+        if not hasattr(self.signature, '__chipflow_uid__'):
+            raise ChipFlowError(f"Signature {self.signature} must be decorated with `sim_annotate()` to use as a simulation model identifier")
 
 
-def cxxmangle(name, ispublic=True):
+def cxxrtlmangle(name, ispublic=True):
     # RTLIL allows any characters in names other than whitespace. This presents an issue for generating C++ code
     # because C++ identifiers may be only alphanumeric, cannot clash with C++ keywords, and cannot clash with cxxrtl
     # identifiers. This issue can be solved with a name mangling scheme. We choose a name mangling scheme that results
@@ -92,47 +95,58 @@ class BasicCxxBuilder(BaseModel):
         cpp_files: C++ files used to define the model
         hpp_files: C++ header files to define the model interfaces
     """
-    models: Dict[str, SimModel]
+    models: List[SimModel]
     cpp_files: List[Path]
     hpp_files: Optional[List[Path]] = None
     hpp_dirs: Optional[List[Path]] = None
 
-    def instantiate_model(self, interface_name: str, sim_interface: SimInterface, interface_desc: Interface, ports: Dict[str, io.SimulationPort]) -> str:
-        name = sim_interface['name']
+    def model_post_init(self, *args, **kwargs):
+        self._table = { getattr(m.signature,'__chipflow_uid__'): m for m in self.models }
+
+    def uid_to_c(self, uid: str) -> str:
+        return uid.replace('.','__')
+
+    def instantiate_model(self, interface: str, sim_interface: SimInterface, interface_desc: Interface, ports: Dict[str, io.SimulationPort]) -> str:
+        #TODO cache if this gets slow
+
+        uid = sim_interface['uid']
         parameters = sim_interface['parameters']
-        if name not in self.models:
+        if uid not in self._table:
             logger.warn(f"Unable to find simulation model for '{sim_interface}'")
 
-        model = self.models[name]
+        model = self._table[uid]
+        print(getattr(model.signature, '__chipflow_uid__'))
         sig = model.signature(**parameters)
         members = list(sig.flatten(sig.create()))
 
         sig_names = [ path for path, _, _ in members ]
         port_names = { n: interface_desc[n].port_name for n in interface_desc.keys()}
 
+        identifier_uid = self.uid_to_c(uid)
         names = [f"\\io${port_names[str(n)]}${d}" for n,d in sig_names]
-        params = [f"top.{cxxmangle(n)}" for n in names]
+        params = [f"top.{cxxrtlmangle(n)}" for n in names]
 
-        out = f"{model.name} {interface_name}(\"{interface_name}\", "
+        out = f"{model.name} {interface}(\"{interface}\", "
         out += ', '.join(list(params))
         out += ')\n'
         return out
 
 def find_builder(builders: List[BasicCxxBuilder], sim_interface: SimInterface):
-    name = sim_interface['name']
+    uid = sim_interface['uid']
     for b in builders:
-        if name in b.models:
+        if uid in b._table:
             return b
-    logger.warn(f"Unable to find builder for '{name}'")
+    logger.warn(f"Unable to find builder for '{uid}'")
     return None
+
 _COMMON_BUILDER = BasicCxxBuilder(
-    models={
-        SPISignature.__name__: SimModel('spi_model', SPISignature),
-        QSPIFlashSignature.__name__: SimModel('spiflash_model', QSPIFlashSignature,  [SimModelCapability.LOAD_DATA]),
-        UARTSignature.__name__: SimModel('uart_model', UARTSignature),
-        I2CSignature.__name__: SimModel('i2c_model', I2CSignature),
-        GPIOSignature.__name__: SimModel('gpio_model', GPIOSignature),
-        },
+    models=[
+        SimModel('spi_model', SPISignature),
+        SimModel('spiflash_model', QSPIFlashSignature,  [SimModelCapability.LOAD_DATA]),
+        SimModel('uart_model', UARTSignature),
+        SimModel('i2c_model', I2CSignature),
+        SimModel('gpio_model', GPIOSignature),
+        ],
     cpp_files=[ Path('{COMMON_DIR}', 'models.cc') ],
     hpp_files=[ Path('models.h') ],
     hpp_dirs=[Path("{COMMON_DIR}")],
@@ -203,8 +217,10 @@ def build(self, e):
                     includes = [hpp for b in self._builders if b.hpp_files for hpp in b.hpp_files ],
                     initialisers = [exp for exp in self._top_sim.values()],
                     interfaces = [exp for exp in self._top_sim.keys()],
-                    clocks = [cxxmangle(f"io${clk}$i") for clk in self._clocks.keys()],
-                    resets = [cxxmangle(f"io${rst}$i") for rst in self._resets.keys()]),
+                    clocks = [cxxrtlmangle(f"io${clk}$i") for clk in self._clocks.keys()],
+                    resets = [cxxrtlmangle(f"io${rst}$i") for rst in self._resets.keys()],
+                    data_load = [{'model_name': 'flash', 'file_name':_ensure_chipflow_root() / 'build'/ 'software'/'software.bin', 'args':[ '0x00100000U' ]}]
+                ),
                 file=main_file)