wip

Author: robtaylor

chipflow_lib/__init__.py

@@ -48,7 +48,7 @@ def _ensure_chipflow_root():
     return _ensure_chipflow_root.root
 
 
-def _parse_config():
+def _parse_config() -> 'ChipFlowConfig':
     """Parse the chipflow.toml configuration file."""
     chipflow_root = _ensure_chipflow_root()
     config_file = Path(chipflow_root) / "chipflow.toml"
@@ -60,17 +60,15 @@ def _parse_config():
         raise ChipFlowError(f"TOML Error found when loading {config_file}: {e.msg} at line {e.lineno}, column {e.colno}")
 
 
-def _parse_config_file(config_file):
+def _parse_config_file(config_file) -> 'ChipFlowConfig':
     """Parse a specific chipflow.toml configuration file."""
-    from .config_models import Config
 
     with open(config_file, "rb") as f:
         config_dict = tomli.load(f)
 
     try:
         # Validate with Pydantic
-        Config.model_validate(config_dict)  # Just validate the config_dict
-        return config_dict  # Return the original dict for backward compatibility
+        return Config.model_validate(config_dict)  # Just validate the config_dict
     except ValidationError as e:
         # Format Pydantic validation errors in a user-friendly way
         error_messages = []
@@ -81,3 +79,6 @@ def _parse_config_file(config_file):
 
         error_str = "\n".join(error_messages)
         raise ChipFlowError(f"Validation error in chipflow.toml:\n{error_str}")
+
+
+from .config_models import Config

chipflow_lib/cli.py

@@ -26,13 +26,14 @@ def run(argv=sys.argv[1:]):
     commands = {}
     commands["pin"] = PinCommand(config)
 
-    for step_name, step_reference in config["chipflow"]["steps"].items():
-        step_cls = _get_cls_by_reference(step_reference, context=f"step `{step_name}`")
-        try:
-            commands[step_name] = step_cls(config)
-        except Exception:
-            raise ChipFlowError(f"Encountered error while initializing step `{step_name}` "
-                              f"using `{step_reference}`")
+    if config.chipflow.steps:
+        for step_name, step_reference in config.chipflow.steps.items():
+            step_cls = _get_cls_by_reference(step_reference, context=f"step `{step_name}`")
+            try:
+                commands[step_name] = step_cls(config)
+            except Exception:
+                raise ChipFlowError(f"Encountered error while initializing step `{step_name}` "
+                                f"using `{step_reference}`")
 
     parser = argparse.ArgumentParser(
         prog="chipflow",

chipflow_lib/config_models.py

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: BSD-2-Clause
 import re
-from typing import Dict, Optional, Literal, Any, List
+from typing import Dict, Optional, Literal, Any, List, TYPE_CHECKING
 
 from pydantic import BaseModel, model_validator, ValidationInfo, field_validator
 
@@ -39,7 +39,7 @@ def validate_pad_dict(cls, v: dict, info: ValidationInfo):
 
 class SiliconConfig(BaseModel):
     """Configuration for silicon in chipflow.toml."""
-    process: Process
+    process: 'Process'
     package: Literal["caravel", "cf20", "pga144"]
     power: Dict[str, Voltage] = {}
     debug: Optional[Dict[str, bool]] = None
@@ -60,11 +60,6 @@ def validate_pad_dicts(cls, v, info: ValidationInfo):
         return v
 
 
-class StepsConfig(BaseModel):
-    """Configuration for steps in chipflow.toml."""
-    silicon: str
-
-
 class ChipFlowConfig(BaseModel):
     """Root configuration for chipflow.toml."""
     project_name: str

chipflow_lib/pin_lock.py

@@ -13,8 +13,7 @@
 
 
 def lock_pins() -> None:
-    # Get the config as dict for backward compatibility with top_components
-    config_dict = _parse_config()
+    config = _parse_config()
 
     # Parse with Pydantic for type checking and strong typing
 
@@ -28,11 +27,11 @@ def lock_pins() -> None:
     print(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}")
 
     # Get package definition from dict instead of Pydantic model
-    package_name = config_dict["chipflow"]["silicon"]["package"]
+    package_name = config.chipflow.silicon.package
     package_def = PACKAGE_DEFINITIONS[package_name]
-    process = config_dict["chipflow"]["silicon"]["process"]
+    process = config.chipflow.silicon.process
 
-    top = top_components(config_dict)
+    top = top_components(config)
 
     # Use the PackageDef to allocate the pins:
     for name, component in top.items():

chipflow_lib/platforms/silicon.py

@@ -60,7 +60,7 @@ def elaborate(self, platform):
 
         heartbeat_buffer = io.Buffer("o", self.ports.heartbeat)
         m.submodules.heartbeat_buffer = heartbeat_buffer
-        m.d.comb += heartbeat_buffer.o.eq(heartbeat_ctr[-1])
+        m.d.comb += heartbeat_buffer.o.eq(heartbeat_ctr[-1])  # type: ignore
         return m
 
 
@@ -71,10 +71,10 @@ def __init__(self,
                  port: Port,
                  *,
                  invert: bool = False):
-        self._direction = io.Direction(port.direction)
+        self._direction = io.Direction(port.iomodel['direction'])
         self._invert = invert
-        self._model = port.model
-        self._pins = port.pins
+        self._iomodel = port.iomodel
+        self._pins = port.pins if port.pins else []
 
         # Initialize signal attributes to None
         self._i = None
@@ -87,20 +87,20 @@ def __init__(self,
         if self._direction in (io.Direction.Output, io.Direction.Bidir):
             self._o = Signal(port.width, name=f"{component}_{name}__o")
         if self._direction is io.Direction.Bidir:
-            if "all_have_oe" in self._options and self._options["all_have_oe"]:
+            if "all_have_oe" in self._iomodel and self._iomodel["all_have_oe"]:
                 self._oe = Signal(port.width, name=f"{component}_{name}__oe", init=-1)
             else:
                 self._oe = Signal(1, name=f"{component}_{name}__oe", init=-1)
         elif self._direction is io.Direction.Output:
             # Always create an _oe for output ports
             self._oe = Signal(1, name=f"{component}_{name}__oe", init=-1)
 
-        logger.debug(f"Created SiliconPlatformPort {name}, width={len(port.pins)},dir{self._direction}")
+        logger.debug(f"Created SiliconPlatformPort {name}, width={len(self._pins)},dir{self._direction}")
 
     def wire(self, m: Module, interface: PureInterface):
-        assert self._direction == interface.signature.direction
+        assert self._direction == interface.signature.direction  #type: ignore
         if hasattr(interface, 'i'):
-            m.d.comb += interface.i.eq(self.i)
+            m.d.comb += interface.i.eq(self.i)  # type: ignore
         for d in ['o', 'oe']:
             if hasattr(interface, d):
                 m.d.comb += getattr(self, d).eq(getattr(interface, d))
@@ -141,16 +141,16 @@ def invert(self):
 
     def __len__(self):
         if self._direction is io.Direction.Input:
-            return len(self._i)
+            return len(self.i)
         if self._direction is io.Direction.Output:
-            return len(self._o)
+            return len(self.o)
         if self._direction is io.Direction.Bidir:
-            assert len(self._i) == len(self._o)
-            if self._options["all_have_oe"]:
-                assert len(self.o) == len(self._oe)
+            assert len(self.i) == len(self.o)
+            if 'all_have_oe' in self._iomodel and self._iomodel["all_have_oe"]:
+                assert len(self.o) == len(self.oe)
             else:
-                assert len(self._oe) == 1
-            return len(self._i)
+                assert len(self.oe) == 1
+            return len(self.i)
         assert False  # :nocov:
 
     def __getitem__(self, key):
@@ -160,7 +160,7 @@ def __getitem__(self, key):
         result._oe = None if self._oe is None else self._oe[key]
         result._invert = self._invert
         result._direction = self._direction
-        result._options = self._options
+        result._iomodel = self._iomodel
         result._pins = self._pins
         return result
 
@@ -171,7 +171,7 @@ def __invert__(self):
         result._oe = self._oe
         result._invert = not self._invert
         result._direction = self._direction
-        result._options = self._options
+        result._iomodel = self._iomodel
         result._pins = self._pins
         return result
 
@@ -183,7 +183,7 @@ def __add__(self, other):
         result._oe = None if direction is io.Direction.Input else Cat(self._oe, other._oe)
         result._invert = self._invert
         result._direction = direction
-        result._options = self._options
+        result._iomodel = self._iomodel
         result._pins = self._pins + other._pins
         return result
 
@@ -194,6 +194,10 @@ def __repr__(self):
 
 
 class IOBuffer(io.Buffer):
+    o: Signal
+    i: Signal
+    oe: Signal
+
     def elaborate(self, platform):
         if not isinstance(self.port, SiliconPlatformPort):
             raise TypeError(f"Cannot elaborate SiliconPlatform buffer with port {self.port!r}")
@@ -224,6 +228,9 @@ def elaborate(self, platform):
 
 
 class FFBuffer(io.FFBuffer):
+    i: Signal
+    o: Signal
+    oe: Signal
     def elaborate(self, platform):
         if not isinstance(self.port, SiliconPlatformPort):
             raise TypeError(f"Cannot elaborate SiliconPlatform buffer with port {self.port!r}")
@@ -268,10 +275,7 @@ def instantiate_ports(self, m: Module):
                 for name, port in v.items():
                     self._ports[port.port_name] = SiliconPlatformPort(component, name, port)
 
-        for clock, name in self._config["chipflow"]["clocks"].items():
-            if name not in pinlock.package.clocks:
-                raise ChipFlowError("Unable to find clock {name} in pinlock")
-
+        for clock, name in self._config.chipflow.clocks.items():
             port_data = pinlock.package.clocks[name]
             port = SiliconPlatformPort(component, name, port_data, invert=True)
             self._ports[name] = port
@@ -283,7 +287,7 @@ def instantiate_ports(self, m: Module):
             setattr(m.submodules, "clk_buffer_" + clock, clk_buffer)
             m.d.comb += ClockSignal().eq(clk_buffer.i)
 
-        for reset, name in self._config["chipflow"]["resets"].items():
+        for reset, name in self._config.chipflow.resets.items():
             port_data = pinlock.package.resets[name]
             port = SiliconPlatformPort(component, name, port_data)
             self._ports[name] = port

chipflow_lib/platforms/utils.py

@@ -14,7 +14,8 @@
 from typing import (
     Any, Dict, List, Set,
     Tuple, Optional, Union, Literal,
-    Annotated, NamedTuple, Self
+    Annotated, NamedTuple, Self,
+    TYPE_CHECKING
 )
 from typing_extensions import (
     TypedDict, Unpack, NotRequired
@@ -34,6 +35,8 @@
 
 from .. import ChipFlowError, _ensure_chipflow_root, _get_cls_by_reference
 
+if TYPE_CHECKING:
+    from ..config_models import Config
 
 __all__ = ['IO_ANNOTATION_SCHEMA', 'IOSignature',
            'OutputIOSignature', 'InputIOSignature', 'BidirIOSignature',
@@ -101,7 +104,7 @@ class IOModel(_IOModelOptions):
     """
 
     width: int
-    direction: NotRequired[Annotated[io.Direction, PlainSerializer(lambda x: x.value)]]
+    direction: Annotated[io.Direction, PlainSerializer(lambda x: x.value)]
 
 def io_annotation_schema():
     class Model(pydantic.BaseModel):
@@ -555,8 +558,34 @@ def _get_package(self) -> Package:
         assert self is not Self
         return Package(type=self)  # type: ignore
 
+    def _allocate_bringup(self, config: 'Config') -> Component:
+        cds = set(config.chipflow.clock_domains) if config.chipflow.clock_domains else set()
+        cds.discard('sync')
+
+        d: Interface = { 'sync-clk': Port(type='clock',
+                                          pins=[self.bringup_pins.core_clock],
+                                          port_name='sync-clk',
+                                          iomodel=IOModel(width=1, direction=io.Direction.Input)
+                                      ),
+                          'sync-rst': Port(type='reset',
+                                           pins=[self.bringup_pins.core_reset],
+                                           port_name='sync-rst',
+                                           iomodel=IOModel(width=1, direction=io.Direction.Input)
+                                      )
+                       }
+        assert config.chipflow.silicon
+        if config.chipflow.silicon.debug and \
+           config.chipflow.silicon.debug['heartbeat']:
+            d['heartbeat'] = Port(type='heartbeat',
+                                  pins=[self.bringup_pins.core_heartbeat],
+                                  port_name='heartbeat',
+                                  iomodel=IOModel(width=1, direction=io.Direction.Output)
+                              )
+        #TODO: JTAG
+        return {'bringup_pins': d}
+
     @abc.abstractmethod
-    def allocate_pins(self, process: 'Process', lockfile: Optional[LockFile]) -> LockFile:
+    def allocate_pins(self, config: 'Config', process: 'Process', lockfile: LockFile|None) -> LockFile:
         """
         Allocate package pins to the registered component.
         Pins should be allocated in the most usable way for *users* of the packaged IC.
@@ -606,8 +635,10 @@ def model_post_init(self, __context):
         self._ordered_pins: List[Pin] = sorted(pins)
         return super().model_post_init(__context)
 
-    def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> LockFile:
+    def allocate_pins(self, config: 'Config', process: 'Process', lockfile: LockFile|None) -> LockFile:
         portmap =  _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+        bringup_pins = self._allocate_bringup(config)
+        portmap.ports['_core']=bringup_pins
         package = self._get_package()
         return LockFile(package=package, process=process, metadata=self._interfaces, port_map=portmap)
 
@@ -687,8 +718,10 @@ def model_post_init(self, __context):
         self._ordered_pins: List[Pin] = sorted(pins)
         return super().model_post_init(__context)
 
-    def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> 'LockFile':
+    def allocate_pins(self, config: 'Config', process: 'Process', lockfile: LockFile|None) -> LockFile:
         portmap = _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+        bringup_pins = self._allocate_bringup(config)
+        portmap.ports['_core']=bringup_pins
         package = self._get_package()
         return LockFile(package=package, process=process, metadata=self._interfaces, port_map=portmap)
 
@@ -898,9 +931,10 @@ def sort_by_quadrant(pins: Set[GAPin]) -> List[Pin]:
 
         return super().model_post_init(__context)
 
-
-    def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> 'LockFile':
+    def allocate_pins(self, config: 'Config', process: 'Process', lockfile: LockFile|None) -> LockFile:
         portmap = _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+        bringup_pins = self._allocate_bringup(config)
+        portmap.ports['_core']=bringup_pins
         package = self._get_package()
         return LockFile(package=package, process=process, metadata=self._interfaces, port_map=portmap)
 
@@ -985,14 +1019,14 @@ def top_components(config):
     result = {}
 
     # First pass: collect component configs
-    for name, conf in config["chipflow"]["top"].items():
+    for name, conf in config.chipflow.top.items():
         if '.' in name:
             assert isinstance(conf, dict)
             logger.debug(f"Config found for {name}")
             component_configs[name.split('.')[0]] = conf
 
     # Second pass: instantiate components
-    for name, ref in config["chipflow"]["top"].items():
+    for name, ref in config.chipflow.top.items():
         if '.' not in name:  # Skip component configs, only process actual components
             cls = _get_cls_by_reference(ref, context=f"top component: {name}")
             if name in component_configs: