clear up remaining type checking issues

Author: robtaylor

chipflow_lib/__init__.py

@@ -48,8 +48,8 @@ def _ensure_chipflow_root():
 
     if os.environ["CHIPFLOW_ROOT"] not in sys.path:
         sys.path.append(os.environ["CHIPFLOW_ROOT"])
-    _ensure_chipflow_root.root = os.environ["CHIPFLOW_ROOT"]
-    return _ensure_chipflow_root.root
+    _ensure_chipflow_root.root = os.environ["CHIPFLOW_ROOT"]  #type: ignore
+    return _ensure_chipflow_root.root  #type: ignore
 
 
 def _parse_config() -> 'Config':
@@ -84,4 +84,7 @@ def _parse_config_file(config_file) -> 'Config':
         error_str = "\n".join(error_messages)
         raise ChipFlowError(f"Validation error in chipflow.toml:\n{error_str}")
 
+def _get_src_loc(src_loc_at=0):
+      frame = sys._getframe(1 + src_loc_at)
+      return (frame.f_code.co_filename, frame.f_lineno)
 

chipflow_lib/pin_lock.py

@@ -5,8 +5,8 @@
 from pathlib import Path
 from pprint import pformat
 
-from chipflow_lib import _parse_config, _ensure_chipflow_root
-from chipflow_lib.platforms import top_components, LockFile, PACKAGE_DEFINITIONS
+from . import _parse_config, _ensure_chipflow_root, ChipFlowError
+from .platforms import top_components, LockFile, PACKAGE_DEFINITIONS
 
 # logging.basicConfig(stream=sys.stdout, level=logging.DEBUG)
 logger = logging.getLogger(__name__)
@@ -27,6 +27,9 @@ def lock_pins() -> None:
     logger.debug(f"Old Lock =\n{pformat(oldlock)}")
     logger.debug(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}")
 
+    if not config.chipflow.silicon:
+        raise ChipFlowError("no [chipflow.silicon] section found in chipflow.toml")
+
     # Get package definition from dict instead of Pydantic model
     package_name = config.chipflow.silicon.package
     package_def = PACKAGE_DEFINITIONS[package_name]

chipflow_lib/platforms/silicon.py

@@ -1,4 +1,5 @@
 # amaranth: UnusedElaboratable=no
+# type: ignore[reportAttributeAccessIssue]
 
 # SPDX-License-Identifier: BSD-2-Clause
 import logging
@@ -275,29 +276,20 @@ def instantiate_ports(self, m: Module):
                 for name, port in v.items():
                     self._ports[port.port_name] = SiliconPlatformPort(component, name, port)
 
-        for clock, name in self._config.chipflow.clocks.items():
-            port_data = pinlock.package.clocks[name]
-            port = SiliconPlatformPort(component, name, port_data, invert=True)
-            self._ports[name] = port
-
-            if clock == 'default':
-                clock = 'sync'
-            setattr(m.domains, clock, ClockDomain(name=clock))
-            clk_buffer = io.Buffer("i", port)
-            setattr(m.submodules, "clk_buffer_" + clock, clk_buffer)
-            m.d.comb += ClockSignal().eq(clk_buffer.i)
-
-        for reset, name in self._config.chipflow.resets.items():
-            port_data = pinlock.package.resets[name]
-            port = SiliconPlatformPort(component, name, port_data)
-            self._ports[name] = port
+        for clock in pinlock.port_map.get_clocks():
+            setattr(m.domains, clock.port_name, ClockDomain(name=clock))
+            clk_buffer = io.Buffer("i", self._ports[clock.port_name])
+            setattr(m.submodules, "clk_buffer_" + clock.port_name, clk_buffer)
+            m.d.comb += ClockSignal().eq(clk_buffer.i)  #type: ignore[reportAttributeAccessIssue]
+
+        for reset in pinlock.port_map.get_clocks():
             rst_buffer = io.Buffer("i", port)
-            setattr(m.submodules, reset, rst_buffer)
-            setattr(m.submodules, reset + "_sync", FFSynchronizer(rst_buffer.i, ResetSignal()))
+            setattr(m.submodules, reset.port_name, rst_buffer)
+            setattr(m.submodules, reset.port_name + "_sync", FFSynchronizer(rst_buffer.i, ResetSignal()))  #type: ignore[reportAttributeAccessIssue]
 
         self.pinlock = pinlock
 
-    def request(self, name=None, **kwargs):
+    def request(self, name, **kwargs):
         if "$" in name:
             raise NameError(f"Reserved character `$` used in pad name `{name}`")
         if name not in self._ports:
@@ -314,10 +306,10 @@ def get_io_buffer(self, buffer):
             raise TypeError(f"Unsupported buffer type {buffer!r}")
 
         if buffer.direction is not io.Direction.Output:
-            result.i = buffer.i
+            result.i = buffer.i  #type: ignore[reportAttributeAccessIssue]
         if buffer.direction is not io.Direction.Input:
-            result.o = buffer.o
-            result.oe = buffer.oe
+            result.o = buffer.o  #type: ignore[reportAttributeAccessIssue]
+            result.oe = buffer.oe  #type: ignore[reportAttributeAccessIssue]
 
         return result
 
@@ -394,13 +386,3 @@ def build(self, elaboratable, name="top"):
             "-o", output_rtlil.replace("\\", "/")
         ])
         return output_rtlil
-
-    def default_clock(m, platform, clock, reset):
-        # Clock generation
-        m.domains.sync = ClockDomain()
-
-        clk = platform.request(clock)
-        m.d.comb += ClockSignal().eq(clk.i)
-        m.submodules.rst_sync = FFSynchronizer(
-            ~platform.request(reset).i,
-            ResetSignal())

chipflow_lib/platforms/sim.py

@@ -4,8 +4,9 @@
 from pathlib import Path
 
 from amaranth import *
-from amaranth.back import rtlil
+from amaranth.back import rtlil  # type: ignore[reportAttributeAccessIssue]
 
+from .. import _get_src_loc
 
 __all__ = ["SimPlatform"]
 
@@ -49,7 +50,7 @@ def is_model_out(field_name):
                 box += f'  wire width {field_width} {"output" if is_model_out(field_name) else "input"} {i} \\{field_name}\n' # noqa: E501
             box += 'end\n\n'
             self.sim_boxes[inst_type] = box
-        return Instance(inst_type, **conns)
+        return Instance(inst_type, src_loc_at=_get_src_loc(), **conns)
 
     def add_monitor(self, inst_type, iface):
         conns = dict(i_clk=ClockSignal(), a_keep=True)
@@ -67,7 +68,7 @@ def add_monitor(self, inst_type, iface):
                 box += f'  wire width {field_width} input {i + 1} \\{field_name}\n'
             box += 'end\n\n'
             self.sim_boxes[inst_type] = box
-        return Instance(inst_type, **conns)
+        return Instance(inst_type, src_loc_at=_get_src_loc(), **conns)
 
     def build(self, e):
         Path(self.build_dir).mkdir(parents=True, exist_ok=True)

chipflow_lib/platforms/utils.py

@@ -446,18 +446,37 @@ def _add_port(self, component: str, interface: str, port_name: str, port: Port):
             self.ports[component][interface] = {}
         self.ports[component][interface][port_name] = port
 
-    def _add_ports(self, component: str, interface: str, ports: Dict[str, Port]):
+    def _add_ports(self, component: str, interface: str, ports: Interface):
         "Internally used by a `PackageDef`"
         if component not in self.ports:
             self.ports[component] = {}
         self.ports[component][interface] = ports
 
-    def get_ports(self, component: str, interface: str) -> Dict[str, Port]:
+    def get_ports(self, component: str, interface: str) -> Interface:
+
         "List the ports allocated in this PortMap for the given `Component` and `Interface`"
         if component not in self.ports:
             raise KeyError(f"'{component}' not found in {self}")
         return self.ports[component][interface]
 
+    def get_clocks(self) -> List[Port]:
+        ret = []
+        for n, c in self.ports.items():
+            for cn, i in c.items():
+                for ni, p in i.items():
+                    if p.type == "clock":
+                        ret.append(i)
+        return ret
+
+    def get_resets(self) -> List[Port]:
+        ret = []
+        for n, c in self.ports.items():
+            for cn, i in c.items():
+                for ni, p in i.items():
+                    if p.type == "reset":
+                        ret.append(i)
+        return ret
+
 
 class LockFile(pydantic.BaseModel):
     """

chipflow_lib/steps/__init__.py

@@ -35,4 +35,4 @@ def build_cli_parser(self, parser):
 
     def run_cli(self, args):
         "Called when this step's is used from `chipflow` command"
-        self.build()
+        ...

chipflow_lib/steps/silicon.py

@@ -69,9 +69,9 @@ def __init__(self, config):
     def build_cli_parser(self, parser):
         action_argument = parser.add_subparsers(dest="action")
         action_argument.add_parser(
-            "prepare", help=inspect.getdoc(self.prepare).splitlines()[0])
+            "prepare", help=inspect.getdoc(self.prepare).splitlines()[0])   # type: ignore
         submit_subparser = action_argument.add_parser(
-            "submit", help=inspect.getdoc(self.submit).splitlines()[0])
+            "submit", help=inspect.getdoc(self.submit).splitlines()[0])  # type: ignore
         submit_subparser.add_argument(
             "--dry-run", help=argparse.SUPPRESS,
             default=False, action="store_true")
@@ -128,7 +128,7 @@ def submit(self, rtlil_path, args):
             fh = None
             submission_name = self.determine_submission_name()
             data = {
-                "projectId": self.project_name,
+                "projectId": self.config.project_name,
                 "name": submission_name,
             }
 
@@ -173,7 +173,7 @@ def network_err(e):
                     fh.close()
                 exit(1)
 
-            sp.info(f"> Submitting {submission_name} for project {self.project_name} to ChipFlow Cloud {self._chipflow_api_origin}")
+            sp.info(f"> Submitting {submission_name} for project {self.config.project_name} to ChipFlow Cloud {self._chipflow_api_origin}")
             sp.start("Sending design to ChipFlow Cloud")
 
             build_submit_url = f"{self._chipflow_api_origin}/build/submit"
@@ -216,7 +216,6 @@ def network_err(e):
 
                 if args.wait:
                     exit_code = self._stream_logs(sp, network_err)
-                sp.ok()
                 if fh:
                     fh.close()
                 exit(exit_code)

pyproject.toml

@@ -49,6 +49,7 @@ typeCheckingMode = "standard"
 reportInvalidTypeForm = false
 reportMissingImports = false
 reportUnboundVariable = false
+reportWildcardImportFromLibrary = false
 
 [tool.ruff]
 include = [
@@ -73,7 +74,7 @@ test.cmd = "pytest"
 test-cov.cmd = "pytest --cov=chipflow_lib --cov-report=term"
 test-cov-html.cmd = "pytest --cov=chipflow_lib --cov-report=html"
 test-docs.cmd = "sphinx-build -b doctest docs/ docs/_build"
-lint.composite = [ "ruff check", "pyrefly check chipflow_lib"]
+lint.composite = [ "ruff check", "pyright chipflow_lib"]
 docs.cmd = "sphinx-build docs/ docs/_build/ -W --keep-going"
 test-silicon.cmd = "pytest tests/test_silicon_platform.py tests/test_silicon_platform_additional.py tests/test_silicon_platform_amaranth.py tests/test_silicon_platform_build.py tests/test_silicon_platform_port.py --cov=chipflow_lib.platforms.silicon --cov-report=term"
 _check-project.call = "tools.check_project:main"