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+50
-48
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8 files changed

+50
-48
lines changed

chipflow_lib/__init__.py

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,10 @@
99
import tomli
1010
from pathlib import Path
1111
from pydantic import ValidationError
12+
from typing import TYPE_CHECKING
13+
14+
if TYPE_CHECKING:
15+
from .config_models import Config
1216

1317
__version__ = importlib.metadata.version("chipflow_lib")
1418

@@ -48,7 +52,7 @@ def _ensure_chipflow_root():
4852
return _ensure_chipflow_root.root
4953

5054

51-
def _parse_config() -> 'ChipFlowConfig':
55+
def _parse_config() -> 'Config':
5256
"""Parse the chipflow.toml configuration file."""
5357
chipflow_root = _ensure_chipflow_root()
5458
config_file = Path(chipflow_root) / "chipflow.toml"
@@ -60,7 +64,7 @@ def _parse_config() -> 'ChipFlowConfig':
6064
raise ChipFlowError(f"TOML Error found when loading {config_file}: {e.msg} at line {e.lineno}, column {e.colno}")
6165

6266

63-
def _parse_config_file(config_file) -> 'ChipFlowConfig':
67+
def _parse_config_file(config_file) -> 'Config':
6468
"""Parse a specific chipflow.toml configuration file."""
6569

6670
with open(config_file, "rb") as f:
@@ -81,4 +85,3 @@ def _parse_config_file(config_file) -> 'ChipFlowConfig':
8185
raise ChipFlowError(f"Validation error in chipflow.toml:\n{error_str}")
8286

8387

84-
from .config_models import Config

chipflow_lib/config_models.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# SPDX-License-Identifier: BSD-2-Clause
22
import re
3-
from typing import Dict, Optional, Literal, Any, List, TYPE_CHECKING
3+
from typing import Dict, Optional, Literal, Any, List
44

55
from pydantic import BaseModel, model_validator, ValidationInfo, field_validator
66

chipflow_lib/pin_lock.py

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,10 @@ def lock_pins() -> None:
2222
oldlock = None
2323

2424
if lockfile.exists():
25+
print("Reusing current pin allocation from `pins.lock`")
2526
oldlock = LockFile.model_validate_json(lockfile.read_text())
26-
print(f"Old Lock =\n{pformat(oldlock)}")
27-
print(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}")
27+
logger.debug(f"Old Lock =\n{pformat(oldlock)}")
28+
logger.debug(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}")
2829

2930
# Get package definition from dict instead of Pydantic model
3031
package_name = config.chipflow.silicon.package
@@ -37,7 +38,7 @@ def lock_pins() -> None:
3738
for name, component in top.items():
3839
package_def.register_component(name, component)
3940

40-
newlock = package_def.allocate_pins(process, oldlock)
41+
newlock = package_def.allocate_pins(config, process, oldlock)
4142

4243
with open(lockfile, 'w') as f:
4344
f.write(newlock.model_dump_json(indent=2, serialize_as_any=True))

chipflow_lib/platforms/utils.py

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66

77

88
from collections import OrderedDict, deque
9-
from collections.abc import MutableMapping
109
from dataclasses import dataclass, asdict
1110
from enum import Enum, IntEnum, StrEnum
1211
from math import ceil, floor
@@ -22,15 +21,13 @@
2221
)
2322

2423

25-
from amaranth import Const, ClockDomain, Fragment
24+
from amaranth import Const
2625
from amaranth.lib import wiring, io, meta
2726
from amaranth.lib.wiring import In, Out
2827
from pydantic import (
2928
ConfigDict, TypeAdapter, PlainSerializer,
30-
WithJsonSchema, with_config,
31-
GetCoreSchemaHandler
29+
WithJsonSchema, with_config
3230
)
33-
from pydantic_core import core_schema, CoreSchema
3431

3532

3633
from .. import ChipFlowError, _ensure_chipflow_root, _get_cls_by_reference
@@ -109,11 +106,9 @@ class IOModel(_IOModelOptions):
109106
def io_annotation_schema():
110107
class Model(pydantic.BaseModel):
111108
data_td: IOModel
112-
print(Model.model_json_schema())
113109

114110
PydanticModel = TypeAdapter(IOModel)
115-
#schema = PydanticModel.json_schema()
116-
schema = Model.model_json_schema()
111+
schema = PydanticModel.json_schema()
117112
schema['$schema'] = "https://json-schema.org/draft/2020-12/schema"
118113
schema['$id'] = IO_ANNOTATION_SCHEMA
119114
return schema

pdm.lock

Lines changed: 24 additions & 25 deletions
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pyproject.toml

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ authors = [
1313
]
1414
license = {file = "LICENSE.md"}
1515

16-
requires-python = ">=3.10"
16+
requires-python = ">=3.11"
1717
dependencies = [
1818
"amaranth[builtin-yosys]>=0.5,<0.7",
1919
"amaranth-soc @ git+https://github.com/amaranth-lang/amaranth-soc",
@@ -29,6 +29,7 @@ dependencies = [
2929
"pydantic>=2.8",
3030
"halo>=0.0.31",
3131
"pyrefly>=0.21.0",
32+
"amaranth-stubs>=0.1.1",
3233
]
3334

3435
[project.scripts]
@@ -72,7 +73,7 @@ test.cmd = "pytest"
7273
test-cov.cmd = "pytest --cov=chipflow_lib --cov-report=term"
7374
test-cov-html.cmd = "pytest --cov=chipflow_lib --cov-report=html"
7475
test-docs.cmd = "sphinx-build -b doctest docs/ docs/_build"
75-
lint.composite = [ "ruff check", "pyrefly check"]
76+
lint.composite = [ "ruff check", "pyrefly check chipflow_lib"]
7677
docs.cmd = "sphinx-build docs/ docs/_build/ -W --keep-going"
7778
test-silicon.cmd = "pytest tests/test_silicon_platform.py tests/test_silicon_platform_additional.py tests/test_silicon_platform_amaranth.py tests/test_silicon_platform_build.py tests/test_silicon_platform_port.py --cov=chipflow_lib.platforms.silicon --cov-report=term"
7879
_check-project.call = "tools.check_project:main"

tests/test_init.py

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
_parse_config_file,
1414
_parse_config
1515
)
16+
from chipflow_lib.config_model import Config, ChipFlowConfig
1617

1718

1819
class TestCoreUtilities(unittest.TestCase):
@@ -104,16 +105,16 @@ def test_parse_config_file_valid(self):
104105

105106
config = _parse_config_file(config_path)
106107

107-
self.assertIn("chipflow", config)
108-
self.assertEqual(config["chipflow"]["project_name"], "test_project")
109-
self.assertEqual(config["chipflow"]["silicon"]["process"], "sky130")
108+
assert config.chipflow
109+
self.assertEqual(config.chipflow.project_name, "test_project")
110+
self.assertEqual(config.chipflow.silicon.process, "sky130")
110111

111112
@mock.patch("chipflow_lib._ensure_chipflow_root")
112113
@mock.patch("chipflow_lib._parse_config_file")
113114
def test_parse_config(self, mock_parse_config_file, mock_ensure_chipflow_root):
114115
"""Test _parse_config which uses _ensure_chipflow_root and _parse_config_file"""
115116
mock_ensure_chipflow_root.return_value = "/mock/chipflow/root"
116-
mock_parse_config_file.return_value = {"chipflow": {"test": "value"}}
117+
mock_parse_config_file.return_value = Config(chipflow=ChipFlowConfig(project_name='test', top={'test','test'}))
117118

118119
config = _parse_config()
119120

@@ -123,4 +124,5 @@ def test_parse_config(self, mock_parse_config_file, mock_ensure_chipflow_root):
123124
if hasattr(mock_parse_config_file.call_args[0][0], 'as_posix')
124125
else mock_parse_config_file.call_args[0][0],
125126
"/mock/chipflow/root/chipflow.toml")
126-
self.assertEqual(config, {"chipflow": {"test": "value"}})
127+
self.assertEqual(config.chipflow.project_name, "test")
128+
self.assertEqual(config.chipflow.project_name.top, {'test': 'test'})

tests/test_utils.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
import logging
33
import pytest #noqa
44

5+
from amaranth import Const
56
from amaranth.lib import io
67

78
from chipflow_lib.platforms.utils import IOSignature, OutputIOSignature, InputIOSignature, BidirIOSignature
@@ -75,7 +76,7 @@ def test_signature_factory_functions():
7576
"""Test the factory functions for creating IOSignatures"""
7677

7778
# Test OutputIOSignature factory
78-
output_sig = OutputIOSignature(width=32, init=0x12345678)
79+
output_sig = OutputIOSignature(width=32, init=Const.cast(0x12345678))
7980
assert output_sig.direction == io.Direction.Output
8081
assert output_sig.width == 32
8182

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