In order to remove the need for users to define their own SiliconStep
and pin layout.This introduces a number of mechanisms:

 - PinSignature: a mechanism for Components to label wiring that should
   be routed to pads/pins and the requriments.
 - Pin lock mechanism: addition of `pins` subcommand to `chipflow` cli
   tool. This inspects the top level components and maps the ports to
   pins, with pin behaviour defined by the package definition.
 - Package definitions - basis for package definitions in chipflow-lib
 - General purpose SiliconStep

Still remaining follow on changes are:
 - Encoding power, clock, heartbeat and jtag pin locations in package
   definitions.
 - Pin lock for FPGA boards
 - Removal of need for user to define other steps (sim, software, board,
   export verilog)