Added process to the pin lock file

chipflow_lib/__init__.py

@@ -80,6 +80,7 @@ def _ensure_chipflow_root():
                     "additionalProperties": False,
                     "properties": {
                         "process": {
+                            "type": "string",
                             "enum": ["sky130", "gf180", "customer1", "gf130bcd", "ihp_sg13g2"]
                         },
                         "package": {

chipflow_lib/pin_lock.py

@@ -86,6 +86,7 @@ def lock_pins() -> None:
         oldlock = LockFile.model_validate_json(json_string)
 
     print(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}")
+    process_name = config["chipflow"]["silicon"]["process"]
     package_name = config["chipflow"]["silicon"]["package"]
 
     if package_name not in PACKAGE_DEFINITIONS:
@@ -145,7 +146,10 @@ def lock_pins() -> None:
                 _map, _ = allocate_pins(k, v, pins)
                 port_map.add_ports(component, k, _map)
 
-    newlock = LockFile(package=package, port_map=port_map, metadata=interfaces)
+    newlock = LockFile(process=process_name,
+                       package=package,
+                       port_map=port_map,
+                       metadata=interfaces)
 
     with open('pins.lock', 'w') as f:
         f.write(newlock.model_dump_json(indent=2, serialize_as_any=True))

chipflow_lib/platforms/utils.py

@@ -396,6 +396,17 @@ def get_ports(self, component: str, name: str) -> Dict[str, Port]:
         return self[component][name]
 
 
+class Process(enum.Enum):
+    SKY130 = "sky130"
+    GF180 = "gf180"
+    HELVELLYN2 = "helvellyn2"
+    GF130BCD = "gf130bcd"
+    IHP_SG13G2 = "ihp_sg13g2"
+
+    def __str__(self):
+        return f'{self.name}'
+
+
 class LockFile(pydantic.BaseModel):
     """
     Representation of a pin lock file.
@@ -405,6 +416,7 @@ class LockFile(pydantic.BaseModel):
         port_map: Mapping of components to interfaces to port
         metadata: Amaranth metadata, for reference
     """
+    process: Process
     package: Package
     port_map: PortMap
     metadata: dict

chipflow_lib/steps/silicon.py

@@ -140,16 +140,15 @@ def submit(self, rtlil_path, *, dry_run=False):
                 for i in range(width):
                     padname = f"{iface}{i}"
                     logger.debug(f"padname={padname}, port={port}, loc={port.pins[i]}, "
-                          f"dir={port.direction}, width={width}")
+                                 f"dir={port.direction}, width={width}")
                     pads[padname] = {'loc': port.pins[i], 'type': port.direction.value}
             else:
                 padname = f"{iface}"
 
                 logger.debug(f"padname={padname}, port={port}, loc={port.pins[0]}, "
-                        f"dir={port.direction}, width={width}")
+                             f"dir={port.direction}, width={width}")
                 pads[padname] = {'loc': port.pins[0], 'type': port.direction.value}
 
-
         config = {
             "dependency_versions": dep_versions,
             "silicon": {

docs/chipflow-toml-guide.rst

@@ -57,12 +57,15 @@ You probably won't need to change these if you're starting from an example repos
 .. code-block:: TOML
 
    [chipflow.silicon]
-   process = "ihp_sg13g2"
+   processes = [
+        "ihp_sg13g2",
+        "gf130bcd"
+        ]
    package = "pga144"
 
 
-The ``silicon`` section sets the Foundry ``process`` we are targeting for manufacturing, and the physical ``package`` we want to place our design inside.
-You'll choose the ``process`` and ``package`` based in the requirements of your design. 
+The ``silicon`` section sets the Foundry ``processes`` (i.e. PDKs) that we are targeting for manufacturing, and the physical ``package`` we want to place our design inside.
+You'll choose the ``processes`` and ``package`` based in the requirements of your design.
 
 Available processes
 -------------------

tests/fixtures/mock.toml

@@ -5,7 +5,11 @@ project_name = "proj-name"
 silicon = "chipflow_lib.steps.silicon:SiliconStep"
 
 [chipflow.silicon]
-process = "ihp_sg13g2"
+processes = [
+  "ihp_sg13g2",
+  "helvellyn2",
+  "sky130"
+]
 package = "pga144"
 
 [chipflow.clocks]