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Updated upcounter design to have top pins be directly specified with PinSignature #6

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Updated upcounter design to have top pins be directly specified with PinSignature #6

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35bc0e7
Updated upcounter design to have top pins be directly specified with …
lanserge May 8, 2025
3f3b652
Removed unused code
lanserge May 8, 2025
f60eae1
Synced with chipflow-lib
lanserge Nov 10, 2025
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35 changes: 2 additions & 33 deletions sram/chipflow.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -7,37 +7,6 @@ soc = "design.design:MySoC"
[chipflow.steps]
silicon = "chipflow_lib.steps.silicon:SiliconStep"

[chipflow.clocks]
default = 'sys_clk'

[chipflow.resets]
default = 'sys_rst_n'

[chipflow.silicon]
process = "ihp_sg13g2"
package = "pga144"

[chipflow.silicon.pads]
# System
sys_clk = { type = "clock", loc = "114" }
sys_rst_n = { type = "reset", loc = "115" }

[chipflow.silicon.power]
dvss0 = { type = "power", loc = "1" }
dvdd0 = { type = "ground", loc = "9" }
vss0 = { type = "power", loc = "17" }
vdd0 = { type = "ground", loc = "25" }
dvss1 = { type = "power", loc = "33" }
dvdd1 = { type = "ground", loc = "41" }
vss1 = { type = "power", loc = "49" }
vdd1 = { type = "ground", loc = "57" }
dvss2 = { type = "power", loc = "65" }
dvdd2 = { type = "ground", loc = "73" }
vss2 = { type = "power", loc = "81" }
vdd2 = { type = "ground", loc = "89" }
dvss3 = { type = "power", loc = "97" }
dvdd3 = { type = "ground", loc = "105" }
vss3 = { type = "power", loc = "113" }
vdd3 = { type = "ground", loc = "121" }
dvss4 = { type = "power", loc = "129" }
dvdd4 = { type = "ground", loc = "137" }
process = "sky130"
package = "openframe"
14 changes: 5 additions & 9 deletions sram/design/design.py
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Original file line number Diff line number Diff line change
@@ -1,17 +1,16 @@
from amaranth import *
from amaranth.lib import wiring
from amaranth.lib.wiring import In, Out, flipped, connect
from chipflow_lib.platforms import InputPinSignature, OutputPinSignature
from chipflow_lib.platforms import InputIOSignature, OutputIOSignature


__all__ = ["SRAMSignature", "SRAM"]

SRAMSignature = wiring.Signature({
"addr": Out(InputPinSignature(12)),
"data_out": Out(OutputPinSignature(16)),
"data_oe": Out(OutputPinSignature(16)),
"data_in": Out(InputPinSignature(16)),
"wr_en": Out(InputPinSignature(1))
"addr": Out(InputIOSignature(12)),
"data_out": Out(OutputIOSignature(8)),
"data_in": Out(InputIOSignature(8)),
"wr_en": Out(InputIOSignature(1))
})


Expand Down Expand Up @@ -46,9 +45,6 @@ def elaborate(self, platform):
with m.Else():
m.d.sync += self.mem.data_out.o.eq(sram_r.data)

for i in range(self.data_width):
m.d.comb += self.mem.data_oe.o[i].eq(self.mem.wr_en.i)

return m


Expand Down
33 changes: 2 additions & 31 deletions upcounter/chipflow.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -7,38 +7,9 @@ soc = "design.design:MySoC"
[chipflow.steps]
silicon = "chipflow_lib.steps.silicon:SiliconStep"

[chipflow.clocks]
default = 'sys_clk'

[chipflow.resets]
default = 'sys_rst_n'

[chipflow.silicon]
process = "ihp_sg13g2"
package = "pga144"

[chipflow.silicon.pads]
# System
sys_clk = { type = "clock", loc = "114" }
sys_rst_n = { type = "reset", loc = "115" }

[chipflow.silicon.power]
dvss0 = { type = "power", loc = "1" }
dvdd0 = { type = "ground", loc = "9" }
vss0 = { type = "power", loc = "17" }
vdd0 = { type = "ground", loc = "25" }
dvss1 = { type = "power", loc = "33" }
dvdd1 = { type = "ground", loc = "41" }
vss1 = { type = "power", loc = "49" }
vdd1 = { type = "ground", loc = "57" }
dvss2 = { type = "power", loc = "65" }
dvdd2 = { type = "ground", loc = "73" }
vss2 = { type = "power", loc = "81" }
vdd2 = { type = "ground", loc = "89" }
dvss3 = { type = "power", loc = "97" }
dvdd3 = { type = "ground", loc = "105" }
vss3 = { type = "power", loc = "113" }
vdd3 = { type = "ground", loc = "121" }
dvss4 = { type = "power", loc = "129" }
dvdd4 = { type = "ground", loc = "137" }
#process = "sky130"
#package = "openframe"

38 changes: 16 additions & 22 deletions upcounter/design/design.py
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Original file line number Diff line number Diff line change
@@ -1,40 +1,34 @@
from amaranth import *
from amaranth.lib import wiring
from amaranth.lib.wiring import In, Out, flipped, connect
from chipflow_lib.platforms import InputPinSignature, OutputPinSignature
from amaranth.lib.wiring import Out
from chipflow_lib.platforms import InputIOSignature, OutputIOSignature

__all__ = ["CounterSignature", "UpCounter"]

CounterSignature = wiring.Signature({
"limit": Out(InputPinSignature(8)),
"en": Out(InputPinSignature(1)),
"ovf": Out(OutputPinSignature(1)),
"count": Out(OutputPinSignature(8))
})
__all__ = ["UpCounter"]


class UpCounter(wiring.Component):
design_name = "upcounter"

def __init__(self):
# define interfaces (for pads connections see design/steps/silicon.py and test_socs_common/silicon.py)
interfaces = {
"pins": Out(CounterSignature),
}
super().__init__(interfaces)
limit: Out(InputIOSignature(8))
en: Out(InputIOSignature(1))
ovf: Out(OutputIOSignature(1))
count: Out(OutputIOSignature(8))

def elaborate(self, platform):
m = Module()

pins = self.pins
limit = self.limit
en = self.en
ovf = self.ovf
count = self.count

m.d.comb += pins.ovf.o.eq(pins.count.o == pins.limit.i)
m.d.comb += ovf.o.eq(count.o == limit.i)

with m.If(pins.en.i):
with m.If(pins.ovf.o):
m.d.sync += pins.count.o.eq(0)
with m.If(en.i):
with m.If(ovf.o):
m.d.sync += count.o.eq(0)
with m.Else():
m.d.sync += pins.count.o.eq(pins.count.o + 1)
m.d.sync += count.o.eq(count.o + 1)

return m

Expand Down
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