Add WAITPKG checks, add support for TPAUSE within SpinPause (microsoft#24524)

### Description
This change introduces `TPAUSE` support in the `SpinPause()` function in
Windows and Linux to reduce power consumption and improve efficiency
during spin-wait periods. `TPAUSE` is a lightweight power/performance
ISA that goes into an optimized C0 power state while waiting on a delay
event, compared to `_mm_pause()` which is a NOP-like instruction that
provides a small delay in the CPU Pipeline. With this change,
performance of First Inference Latency across certain models can also
improve. Models that were tested internally have shown up to ~2x
improvement in First Inference Latency and up to ~20% lower overall
power consumption.

Genuine Intel CPUID detection logic was also refactored into a shared
utility (`CheckIntel()`), enabling consistent platform checks across the
codebase. Here `TPAUSE` is enabled by default for architectures that
support it.

[Intel Intrinsics Guide
(TPAUSE)](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=tpause&techs=MMX,SSE_ALL,AVX_ALL,AVX_512,AMX,SVML,Other&ig_expand=6888,6888)

### Motivation and Context
Performance and power efficiency gains - Previous PR was created which
initially introduced the TPAUSE instruction in `SpinPause()` with
measured improvements in power (please see previous TPAUSE PR here: [Add
WAITPKG checks, add support for TPAUSE in ThreadPool spin
microsoft#16935](microsoft#16935)).
Additional performance testing and measurements were done across Mobile,
Desktop, and Server, influencing enhancements to the PR such as a tweak
to the `spin_delay_cycles`, Linux support and the refactored Intel CPUID
detection logic.

Author: omarhass47

cmake/CMakeLists.txt

@@ -258,7 +258,6 @@ option(onnxruntime_USE_OPENVINO_INTERFACE "Build ONNXRuntime shared lib which is
 option(onnxruntime_USE_VITISAI_INTERFACE "Build ONNXRuntime shared lib which is compatible with Vitis-AI EP interface" OFF)
 option(onnxruntime_USE_QNN_INTERFACE "Build ONNXRuntime shared lib which is compatible with QNN EP interface" OFF)
 
-
 if("${CMAKE_C_COMPILER_ID}" STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_LESS 11.1)
   message(FATAL_ERROR  "GCC version must be greater than or equal to 11.1")
 endif()

cmake/onnxruntime_common.cmake

@@ -11,6 +11,8 @@ set(onnxruntime_common_src_patterns
     "${ONNXRUNTIME_ROOT}/core/common/logging/*.cc"
     "${ONNXRUNTIME_ROOT}/core/common/logging/sinks/*.h"
     "${ONNXRUNTIME_ROOT}/core/common/logging/sinks/*.cc"
+    "${ONNXRUNTIME_ROOT}/core/platform/check_intel.h"
+    "${ONNXRUNTIME_ROOT}/core/platform/check_intel.cc"
     "${ONNXRUNTIME_ROOT}/core/platform/device_discovery.h"
     "${ONNXRUNTIME_ROOT}/core/platform/device_discovery.cc"
     "${ONNXRUNTIME_ROOT}/core/platform/env.h"
@@ -100,6 +102,14 @@ if(WIN32)
     target_compile_options(onnxruntime_common PRIVATE "/Zc:char8_t-")
   endif()
 endif()
+
+if(NOT WIN32 AND NOT APPLE AND NOT ANDROID AND CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64")
+    set_source_files_properties(
+      ${ONNXRUNTIME_ROOT}/core/common/spin_pause.cc
+      PROPERTIES COMPILE_FLAGS "-mwaitpkg"
+    )
+endif()
+
 if (onnxruntime_USE_TELEMETRY)
   set_target_properties(onnxruntime_common PROPERTIES COMPILE_FLAGS "/FI${ONNXRUNTIME_INCLUDE_DIR}/core/platform/windows/TraceLoggingConfigPrivate.h")
 endif()

include/onnxruntime/core/common/spin_pause.h

@@ -3,26 +3,11 @@
 
 #pragma once
 
-#if defined(_M_AMD64)
-#include <intrin.h>
-#endif
-
-#if defined(__x86_64__)
-#include <xmmintrin.h>
-#endif
-
 namespace onnxruntime {
-
 namespace concurrency {
 
 // Intrinsic to use in spin-loops
-
-inline void SpinPause() {
-#if defined(_M_AMD64) || defined(__x86_64__)
-  _mm_pause();
-#endif
-}
+void SpinPause();
 
 }  // namespace concurrency
-
 }  // namespace onnxruntime

onnxruntime/core/common/cpuid_info.cc

@@ -3,9 +3,12 @@
 #include "core/common/cpuid_info.h"
 #include "core/common/logging/logging.h"
 #include "core/common/logging/severity.h"
+#include "core/platform/check_intel.h"
 
 #ifdef __linux__
-
+#if (defined(_M_AMD64) || defined(__x86_64__)) && !defined(__ANDROID__)
+#include <x86intrin.h>
+#endif
 #include <unistd.h>
 #include <sys/syscall.h>
 #if !defined(__NR_getcpu)
@@ -133,6 +136,17 @@ void CPUIDInfo::X86Init() {
         // avx512_skylake = avx512f | avx512vl | avx512cd | avx512bw | avx512dq
         has_avx512_skylake_ = has_avx512 && (data[1] & ((1 << 16) | (1 << 17) | (1 << 28) | (1 << 30) | (1 << 31)));
         is_hybrid_ = (data[3] & (1 << 15));
+        // Check for TPAUSE
+        CheckIntelResult check_intel = CheckIntel();
+        if (check_intel.is_intel) {
+#ifdef __linux__
+#if !defined(__ANDROID__)
+          has_tpause_ = __builtin_cpu_supports("waitpkg") != 0;
+#endif
+#else
+          has_tpause_ = (data[2] & (1 << 5)) != 0;
+#endif
+        }
         if (max_SubLeaves >= 1) {
           GetCPUID(7, 1, data);
           has_avx512_bf16_ = has_avx512 && (data[0] & (1 << 5));

onnxruntime/core/common/cpuid_info.h

@@ -33,6 +33,7 @@ class CPUIDInfo {
   bool HasSSE3() const { return has_sse3_; }
   bool HasSSE4_1() const { return has_sse4_1_; }
   bool IsHybrid() const { return is_hybrid_; }
+  bool HasTPAUSE() const { return has_tpause_; }
 
   // ARM
   bool HasArmNeonDot() const { return has_arm_neon_dot_; }
@@ -112,6 +113,7 @@ class CPUIDInfo {
   bool has_sse3_{false};
   bool has_sse4_1_{false};
   bool is_hybrid_{false};
+  bool has_tpause_{false};
 
   std::vector<uint32_t> core_uarchs_;  // micro-arch of each core
 

onnxruntime/core/common/spin_pause.cc

@@ -0,0 +1,48 @@
+// Copyright (c) Microsoft Corporation. All rights reserved.
+// Licensed under the MIT License.
+
+#include "core/common/spin_pause.h"
+
+#if defined(_M_AMD64)
+#include <intrin.h>
+#endif
+
+#if defined(__x86_64__)
+#include <xmmintrin.h>
+#endif
+
+#if defined(_M_AMD64) || defined(__x86_64__)
+#include "core/common/cpuid_info.h"
+#if defined(__linux__)
+#include <x86intrin.h>
+#include <immintrin.h>
+#endif
+#endif
+
+namespace onnxruntime {
+namespace concurrency {
+
+// Intrinsic to use in spin-loops
+void SpinPause() {
+#if (defined(_M_AMD64) || defined(__x86_64__)) && \
+    !defined(__ANDROID__) &&                      \
+    !defined(__APPLE__)
+
+  static const bool has_tpause = CPUIDInfo::GetCPUIDInfo().HasTPAUSE();
+  static constexpr uint64_t tpause_spin_delay_cycles = 1000;
+  if (has_tpause) {
+#if defined(_WIN32)
+    _tpause(0x0, __rdtsc() + tpause_spin_delay_cycles);
+#elif defined(__linux__)
+    __builtin_ia32_tpause(0x0, __rdtsc() + tpause_spin_delay_cycles);
+#else
+    _mm_pause();
+#endif
+  } else {
+    _mm_pause();
+  }
+#endif
+}
+
+}  // namespace concurrency
+}  // namespace onnxruntime

onnxruntime/core/platform/check_intel.cc

@@ -0,0 +1,97 @@
+// Copyright (c) Microsoft Corporation. All rights reserved.
+// Licensed under the MIT License.
+
+#include "core/platform/check_intel.h"
+
+#if (defined(_M_AMD64) || defined(__x86_64__))
+#if defined(__linux__)
+#include <cpuid.h>
+#elif defined(_WIN32)
+#include <intrin.h>
+#endif
+#endif
+
+namespace onnxruntime {
+
+CheckIntelResult CheckIntel() {
+  CheckIntelResult intel_check = {false, false};
+  bool is_intel = false;
+  bool is_intel_specified_platform = false;
+
+#if (defined(_M_AMD64) || defined(__x86_64__))
+#if defined(_WIN32)
+  constexpr unsigned int kVendorID_Intel[] = {0x756e6547, 0x6c65746e, 0x49656e69};  // "GenuntelineI"
+  constexpr unsigned int kVendorID_IntelSpecifiedPlatformIDs[] = {
+      // ExtendedModel, ExtendedFamily, Family Code, and Model Number
+      0xa06a,  // MTL
+      0xc065,  // ARL-H
+      0xb065   // ARL-U
+  };
+
+  int regs_leaf0[4];
+  int regs_leaf1[4];
+  __cpuid(regs_leaf0, 0);
+  __cpuid(regs_leaf1, 0x1);
+
+  is_intel =
+      (kVendorID_Intel[0] == static_cast<unsigned int>(regs_leaf0[1])) &&
+      (kVendorID_Intel[1] == static_cast<unsigned int>(regs_leaf0[2])) &&
+      (kVendorID_Intel[2] == static_cast<unsigned int>(regs_leaf0[3]));
+
+  if (!is_intel) {
+    return intel_check;  // if not an Intel CPU, return early
+  }
+
+  for (auto intel_specified_platform : kVendorID_IntelSpecifiedPlatformIDs) {
+    if ((static_cast<unsigned int>(regs_leaf1[0]) >> 4) == intel_specified_platform) {
+      is_intel_specified_platform = true;
+      break;
+    }
+  }
+
+#elif defined(__linux__)
+  constexpr unsigned int kVendorID_Intel[] = {0x756e6547, 0x6c65746e, 0x49656e69};  // "GenuntelineI"
+  unsigned int regs[4] = {0};
+  __get_cpuid(0, &regs[0], &regs[1], &regs[2], &regs[3]);
+
+  is_intel = (regs[1] == kVendorID_Intel[0] &&
+              regs[2] == kVendorID_Intel[1] &&
+              regs[3] == kVendorID_Intel[2]);
+  if (!is_intel) {
+    return intel_check;  // if not an Intel CPU, return early
+  }
+
+  __get_cpuid(1, &regs[0], &regs[1], &regs[2], &regs[3]);
+
+  unsigned int base_family = (regs[0] >> 8) & 0xF;
+  unsigned int base_model = (regs[0] >> 4) & 0xF;
+  unsigned int extended_model = (regs[0] >> 16) & 0xF;
+
+  unsigned int model =
+      (base_family == 0x6 || base_family == 0xF)
+          ? (base_model + (extended_model << 4))
+          : base_model;
+
+  constexpr unsigned int kVendorID_IntelSpecifiedPlatformIDs[] = {
+      // ExtendedModel, ExtendedFamily, Family Code, and Model Number
+      170,  // MTL (0xAA)
+      197,  // ARL-H (0xC5)
+      198   // ARL-U (0xC6)
+  };
+
+  for (auto id : kVendorID_IntelSpecifiedPlatformIDs) {
+    if (model == id) {
+      is_intel_specified_platform = true;
+      break;
+    }
+  }
+#endif  //__linux__
+#endif  // (_M_AMD64) || (__x86_64__)
+
+  intel_check.is_intel = is_intel;
+  intel_check.is_intel_specified_platform = is_intel_specified_platform;
+
+  return intel_check;
+}
+
+}  // namespace onnxruntime

onnxruntime/core/platform/check_intel.h

@@ -0,0 +1,13 @@
+// Copyright (c) Microsoft Corporation. All rights reserved.
+// Licensed under the MIT License.
+
+#pragma once
+
+namespace onnxruntime {
+typedef struct {
+  bool is_intel;
+  bool is_intel_specified_platform;
+} CheckIntelResult;
+
+CheckIntelResult CheckIntel();
+}  // namespace onnxruntime

onnxruntime/core/platform/windows/hardware_core_enumerator.cc

@@ -3,6 +3,7 @@
 
 #include "hardware_core_enumerator.h"
 #include "core/platform/windows/env.h"
+#include "core/platform/check_intel.h"
 #include <memory>
 #include <Windows.h>
 #include <assert.h>
@@ -85,30 +86,11 @@ uint32_t HardwareCoreEnumerator::DefaultIntraOpNumThreads() {
   // # of logical cores = # of P cores x 2 (if hyper threading is enabled) + # of E cores + # of Soc Cores.
   auto cores = GetCoreInfo();
 #if !defined(_M_ARM64EC) && !defined(_M_ARM64) && !defined(__aarch64__)
-  const int kVendorID_Intel[3] = {0x756e6547, 0x6c65746e, 0x49656e69};  // "GenuntelineI"
-  bool isIntelSpecifiedPlatform = false;
-  const int kVendorID_IntelSpecifiedPlatformIDs[3] = {
-      // ExtendedModel, ExtendedFamily, Family Code, and Model Number
-      0xa06a,  // MTL
-      0xc065,  // ARL-H
-      0xb065   // ARL-U
-  };
-
-  int regs_leaf0[4];
-  int regs_leaf1[4];
-  __cpuid(regs_leaf0, 0);
-  __cpuid(regs_leaf1, 0x1);
-
-  auto isIntel = (kVendorID_Intel[0] == regs_leaf0[1]) && (kVendorID_Intel[1] == regs_leaf0[2]) && (kVendorID_Intel[2] == regs_leaf0[3]);
-
-  for (int intelSpecifiedPlatform : kVendorID_IntelSpecifiedPlatformIDs) {
-    if ((regs_leaf1[0] >> 4) == intelSpecifiedPlatform) {
-      isIntelSpecifiedPlatform = true;
-    }
-  }
 
-  if (isIntel) {
-    if (isIntelSpecifiedPlatform) {
+  CheckIntelResult check_intel = CheckIntel();
+
+  if (check_intel.is_intel) {
+    if (check_intel.is_intel_specified_platform) {
       // We want to exclude cores without an LLC
       return cores.LLCCores;
     } else {