suppress iverilog synth warnings in simulation

Oron Port · Oron Port · commit 44e69702b4fb · 2025-04-27T22:22:25.000+03:00
diff --git a/lib/src/main/scala/dfhdl/tools/toolsCore/IcarusVerilog.scala b/lib/src/main/scala/dfhdl/tools/toolsCore/IcarusVerilog.scala
@@ -59,7 +59,12 @@ object IcarusVerilog extends VerilogLinter, VerilogSimulator:
   ): Option[Tool.ProcessLogger] = Some(
     Tool.ProcessLogger(
       lineIsWarning = (line: String) => line.contains("warning: "),
-      lineIsSuppressed = (line: String) => false
+      lineIsSuppressed = (line: String) =>
+        // suppress the "cannot be synthesized" warning when in simulation
+        if (line.contains("cannot be synthesized") && getSet.designDB.inSimulation)
+          true
+        else
+          false
     )
   )
 end IcarusVerilog

Original file line number	Diff line number	Diff line change
`@@ -59,7 +59,12 @@ object IcarusVerilog extends VerilogLinter, VerilogSimulator:`
`59`	`59`	`): Option[Tool.ProcessLogger] = Some(`
`60`	`60`	`Tool.ProcessLogger(`
`61`	`61`	`lineIsWarning = (line: String) => line.contains("warning: "),`
`62`		`- lineIsSuppressed = (line: String) => false`
	`62`	`+ lineIsSuppressed = (line: String) =>`
	`63`	`+ // suppress the "cannot be synthesized" warning when in simulation`
	`64`	`+ if (line.contains("cannot be synthesized") && getSet.designDB.inSimulation)`
	`65`	`+ true`
	`66`	`+ else`
	`67`	`+ false`
`63`	`68`	`)`
`64`	`69`	`)`
`65`	`70`	`end IcarusVerilog`