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Commit 48951d1

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author
Oron Port
committed
fix vhdl'93 std_logic_vector to opaque conversion
1 parent f5ddf87 commit 48951d1

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6 files changed

+224
-164
lines changed

6 files changed

+224
-164
lines changed

‎compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLTypePrinter.scala‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -348,8 +348,10 @@ protected trait VHDLTypePrinter extends AbstractTypePrinter:
348348
def csDFOpaqueConvFuncsBody(dfType: DFOpaque): String =
349349
val typeName = csDFOpaqueTypeName(dfType)
350350
s"""|function to_${typeName}(A : std_logic_vector) return ${typeName} is
351+
| variable A0 : std_logic_vector(A'length - 1 downto 0);
351352
|begin
352-
| return ${printer.csBitsToType(dfType.actualType, "A")};
353+
| A0 := A;
354+
| return ${printer.csBitsToType(dfType.actualType, "A0")};
353355
|end;""".stripMargin
354356
def csDFStructTypeName(dfType: DFStruct): String = s"t_struct_${dfType.name}"
355357
def csDFStructDcl(dfType: DFStruct): String =

‎compiler/stages/src/test/scala/StagesSpec/PrintVHDLCodeSpec.scala‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -511,8 +511,10 @@ class PrintVHDLCodeSpec extends StageSpec:
511511
| end;
512512
| subtype t_opaque_Foo is t_arrX2_std_logic_vector(0 to 9)(0 to 15)(11 downto 0);
513513
| function to_t_opaque_Foo(A : std_logic_vector) return t_opaque_Foo is
514+
| variable A0 : std_logic_vector(A'length - 1 downto 0);
514515
| begin
515-
| return to_t_arrX2_std_logic_vector(A, 10, 16, 12);
516+
| A0 := A;
517+
| return to_t_arrX2_std_logic_vector(A0, 10, 16, 12);
516518
| end;
517519
| signal v : t_opaque_Foo;
518520
|begin
@@ -1230,7 +1232,7 @@ class PrintVHDLCodeSpec extends StageSpec:
12301232
| println("These are the values: " & to_string(param3) & ", " & to_string(param4) & ", " & to_string(param5) & ", " & to_string(param6) & ", " & to_string(param7) & ", " & to_string(param8) & ", " & to_string(param9) & ", " & t_enum_MyEnum'image(param10) & "");
12311233
| report
12321234
| "Debug at Foo" & LF &
1233-
| "compiler/stages/src/test/scala/StagesSpec/PrintVHDLCodeSpec.scala:1176:9" & LF &
1235+
| "compiler/stages/src/test/scala/StagesSpec/PrintVHDLCodeSpec.scala:1178:9" & LF &
12341236
| "param3 = " & to_string(param3) & LF &
12351237
| "param4 = " & to_string(param4) & LF &
12361238
| "param5 = " & to_string(param5) & LF &
@@ -1292,7 +1294,7 @@ class PrintVHDLCodeSpec extends StageSpec:
12921294
| println("These are the values: " & to_string(param3) & ", " & to_string(param4) & ", " & to_string(param5) & ", " & to_string(param6) & ", " & to_string(param7) & ", " & to_string(param8) & ", " & to_string(param9) & ", " & t_enum_MyEnum'image(param10) & "");
12931295
| report
12941296
| "Debug at Foo" & LF &
1295-
| "compiler/stages/src/test/scala/StagesSpec/PrintVHDLCodeSpec.scala:1176:9" & LF &
1297+
| "compiler/stages/src/test/scala/StagesSpec/PrintVHDLCodeSpec.scala:1178:9" & LF &
12961298
| "param3 = " & to_string(param3) & LF &
12971299
| "param4 = " & to_string(param4) & LF &
12981300
| "param5 = " & to_string(param5) & LF &

‎lib/src/test/resources/ref/AES.CipherSpecNoOpaques/vhdl.v2008/hdl/CipherNoOpaques_pkg.vhd‎

Lines changed: 46 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ constant sboxLookupTable : t_arrX1_std_logic_vector(0 to 255)(7 downto 0) := (
6868
240 => x"8c", 241 => x"a1", 242 => x"89", 243 => x"0d", 244 => x"bf", 245 => x"e6", 246 => x"42", 247 => x"68",
6969
248 => x"41", 249 => x"99", 250 => x"2d", 251 => x"0f", 252 => x"b0", 253 => x"54", 254 => x"bb", 255 => x"16"
7070
);
71-
constant Rcon : t_arrX1_t_opaque_AESWord(0 to 10) := (
71+
constant Rcon : t_arrX1_t_opaque_AESWord(0 to 10) := (
7272
0 => (0 => x"00", 1 => x"00", 2 => x"00", 3 => x"00"), 1 => (0 => x"01", 1 => x"00", 2 => x"00", 3 => x"00"),
7373
2 => (0 => x"02", 1 => x"00", 2 => x"00", 3 => x"00"), 3 => (0 => x"04", 1 => x"00", 2 => x"00", 3 => x"00"),
7474
4 => (0 => x"08", 1 => x"00", 2 => x"00", 3 => x"00"), 5 => (0 => x"10", 1 => x"00", 2 => x"00", 3 => x"00"),
@@ -80,42 +80,56 @@ end package CipherNoOpaques_pkg;
8080

8181
package body CipherNoOpaques_pkg is
8282
function to_t_opaque_AESByte(A : std_logic_vector) return t_opaque_AESByte is
83+
variable A0 : std_logic_vector(A'length - 1 downto 0);
8384
begin
84-
return A;
85+
A0 := A;
86+
return A0;
8587
end;
8688
function to_t_opaque_AESWord(A : std_logic_vector) return t_opaque_AESWord is
89+
variable A0 : std_logic_vector(A'length - 1 downto 0);
8790
begin
88-
return to_t_arrX1_t_opaque_AESByte(A, 4);
91+
A0 := A;
92+
return to_t_arrX1_t_opaque_AESByte(A0, 4);
8993
end;
9094
function to_t_opaque_AESKey(A : std_logic_vector) return t_opaque_AESKey is
95+
variable A0 : std_logic_vector(A'length - 1 downto 0);
9196
begin
92-
return to_t_arrX1_t_opaque_AESWord(A, 4);
97+
A0 := A;
98+
return to_t_arrX1_t_opaque_AESWord(A0, 4);
9399
end;
94100
function to_t_opaque_AESData(A : std_logic_vector) return t_opaque_AESData is
101+
variable A0 : std_logic_vector(A'length - 1 downto 0);
95102
begin
96-
return to_t_arrX1_t_opaque_AESWord(A, 4);
103+
A0 := A;
104+
return to_t_arrX1_t_opaque_AESWord(A0, 4);
97105
end;
98106
function to_t_opaque_AESKeySchedule(A : std_logic_vector) return t_opaque_AESKeySchedule is
107+
variable A0 : std_logic_vector(A'length - 1 downto 0);
99108
begin
100-
return to_t_arrX1_t_opaque_AESWord(A, 44);
109+
A0 := A;
110+
return to_t_arrX1_t_opaque_AESWord(A0, 44);
101111
end;
102112
function to_t_opaque_AESState(A : std_logic_vector) return t_opaque_AESState is
113+
variable A0 : std_logic_vector(A'length - 1 downto 0);
103114
begin
104-
return to_t_arrX1_t_opaque_AESWord(A, 4);
115+
A0 := A;
116+
return to_t_arrX1_t_opaque_AESWord(A0, 4);
105117
end;
106118
function to_t_opaque_AESRoundKey(A : std_logic_vector) return t_opaque_AESRoundKey is
119+
variable A0 : std_logic_vector(A'length - 1 downto 0);
107120
begin
108-
return to_t_arrX1_t_opaque_AESWord(A, 4);
121+
A0 := A;
122+
return to_t_arrX1_t_opaque_AESWord(A0, 4);
109123
end;
110124
function bitWidth(A : t_arrX1_std_logic_vector) return integer is
111125
begin
112126
return A'length * bitWidth(A(0));
113127
end;
114128
function to_slv(A : t_arrX1_std_logic_vector) return std_logic_vector is
115-
variable hi : integer;
116-
variable lo : integer;
117-
variable cellBitWidth : integer;
118-
variable ret : std_logic_vector(bitWidth(A) - 1 downto 0);
129+
variable hi : integer;
130+
variable lo : integer;
131+
variable cellBitWidth: integer;
132+
variable ret : std_logic_vector(bitWidth(A) - 1 downto 0);
119133
begin
120134
cellBitWidth := bitWidth(A(0));
121135
lo := bitWidth(A);
@@ -126,10 +140,10 @@ begin
126140
return ret;
127141
end;
128142
function to_t_arrX1_std_logic_vector(A : std_logic_vector; D1 : integer; D0 : integer) return t_arrX1_std_logic_vector is
129-
variable hi : integer;
130-
variable lo : integer;
131-
variable cellBitWidth : integer;
132-
variable ret : t_arrX1_std_logic_vector(0 to D1 - 1)(D0 - 1 downto 0);
143+
variable hi : integer;
144+
variable lo : integer;
145+
variable cellBitWidth: integer;
146+
variable ret : t_arrX1_std_logic_vector(0 to D1 - 1)(D0 - 1 downto 0);
133147
begin
134148
cellBitWidth := bitWidth(ret(0));
135149
lo := A'high + 1;
@@ -152,10 +166,10 @@ begin
152166
return A'length * bitWidth(A(0));
153167
end;
154168
function to_slv(A : t_arrX1_t_opaque_AESByte) return std_logic_vector is
155-
variable hi : integer;
156-
variable lo : integer;
157-
variable cellBitWidth : integer;
158-
variable ret : std_logic_vector(bitWidth(A) - 1 downto 0);
169+
variable hi : integer;
170+
variable lo : integer;
171+
variable cellBitWidth: integer;
172+
variable ret : std_logic_vector(bitWidth(A) - 1 downto 0);
159173
begin
160174
cellBitWidth := bitWidth(A(0));
161175
lo := bitWidth(A);
@@ -166,10 +180,10 @@ begin
166180
return ret;
167181
end;
168182
function to_t_arrX1_t_opaque_AESByte(A : std_logic_vector; D1 : integer) return t_arrX1_t_opaque_AESByte is
169-
variable hi : integer;
170-
variable lo : integer;
171-
variable cellBitWidth : integer;
172-
variable ret : t_arrX1_t_opaque_AESByte(0 to D1 - 1);
183+
variable hi : integer;
184+
variable lo : integer;
185+
variable cellBitWidth: integer;
186+
variable ret : t_arrX1_t_opaque_AESByte(0 to D1 - 1);
173187
begin
174188
cellBitWidth := bitWidth(ret(0));
175189
lo := A'high + 1;
@@ -192,10 +206,10 @@ begin
192206
return A'length * bitWidth(A(0));
193207
end;
194208
function to_slv(A : t_arrX1_t_opaque_AESWord) return std_logic_vector is
195-
variable hi : integer;
196-
variable lo : integer;
197-
variable cellBitWidth : integer;
198-
variable ret : std_logic_vector(bitWidth(A) - 1 downto 0);
209+
variable hi : integer;
210+
variable lo : integer;
211+
variable cellBitWidth: integer;
212+
variable ret : std_logic_vector(bitWidth(A) - 1 downto 0);
199213
begin
200214
cellBitWidth := bitWidth(A(0));
201215
lo := bitWidth(A);
@@ -206,10 +220,10 @@ begin
206220
return ret;
207221
end;
208222
function to_t_arrX1_t_opaque_AESWord(A : std_logic_vector; D1 : integer) return t_arrX1_t_opaque_AESWord is
209-
variable hi : integer;
210-
variable lo : integer;
211-
variable cellBitWidth : integer;
212-
variable ret : t_arrX1_t_opaque_AESWord(0 to D1 - 1);
223+
variable hi : integer;
224+
variable lo : integer;
225+
variable cellBitWidth: integer;
226+
variable ret : t_arrX1_t_opaque_AESWord(0 to D1 - 1);
213227
begin
214228
cellBitWidth := bitWidth(ret(0));
215229
lo := A'high + 1;

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