add finish command

Author: Oron Port

compiler/ir/src/main/scala/dfhdl/compiler/ir/DFMember.scala

@@ -1560,7 +1560,7 @@ object TextOut:
   enum Severity derives CanEqual:
     case Info, Warning, Error, Fatal
   enum Op extends HasRefCompare[Op] derives CanEqual:
-    case Print, Println, Debug
+    case Print, Println, Debug, Finish
     case Report(severity: Severity) extends Op
     case Assert(assertionRef: AssertionRef, severity: Severity) extends Op
     lazy val getRefs: List[DFRef.TwoWayAny] = this match

compiler/ir/src/main/scala/dfhdl/compiler/printing/Printer.scala

@@ -329,6 +329,7 @@ class DFPrinter(using val getSet: MemberGetSet, val printerOptions: PrinterOptio
           ).mkString.emptyOr(m => s"s\"$m\"")
       end match
     textOut.op match
+      case TextOut.Op.Finish => "finish()"
       case TextOut.Op.Report(severity) =>
         val csSeverity = if (severity == TextOut.Severity.Info) "" else s", Severity.${severity}"
         s"report($msg$csSeverity)"
@@ -393,7 +394,7 @@ class DFPrinter(using val getSet: MemberGetSet, val printerOptions: PrinterOptio
   val dfhdlKW: Set[String] =
     Set("VAR", "REG", "din", "IN", "OUT", "INOUT", "VAL", "DFRET", "CONST", "DFDesign", "RTDesign",
       "EDDesign", "DFDomain", "RTDomain", "EDDomain", "process", "forever", "all", "init", "step",
-      "goto", "wait", "assert", "report", "print", "println", "debug")
+      "goto", "wait", "assert", "report", "print", "println", "debug", "finish")
   val dfhdlOps: Set[String] = Set("<>", ":=", ":==")
   val dfhdlTypes: Set[String] =
     Set("Bit", "Boolean", "Int", "UInt", "SInt", "Bits", "X", "Encoded", "Struct", "Opaque",

compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogPrinter.scala

@@ -126,6 +126,7 @@ class VerilogPrinter(val dialect: VerilogDialect)(using
     def csDisplay(severity: TextOut.Severity, msg: String) =
       s"""$$display("${severity.toString.toUpperCase()}: ", $msg);${csFinish(severity)}"""
     textOut.op match
+      case TextOut.Op.Finish => "$finish;"
       case TextOut.Op.Report(severity) =>
         if (assertIsSupported) s"${csSeverity(severity)}($msg);"
         else csDisplay(severity, msg)

compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLPrinter.scala

@@ -123,6 +123,7 @@ class VHDLPrinter(val dialect: VHDLDialect)(using
         case TextOut.Severity.Error   => "ERROR"
         case TextOut.Severity.Fatal   => "FAILURE"
     textOut.op match
+      case TextOut.Op.Finish           => "std.env.finish;"
       case TextOut.Op.Report(severity) => csReport(severity, msg)
       case TextOut.Op.Assert(assertionRef, severity) =>
         if (msg.isEmpty)

core/src/main/scala/dfhdl/core/TextOut.scala

@@ -24,13 +24,16 @@ object TextOut:
           severity: Severity
       )(using DFC): ir.TextOut.Op =
         ir.TextOut.Op.Assert(assertion.asIR.refTW[ir.TextOut], severity)
-    export ir.TextOut.Op.{Print, Println, Report, Debug}
+    export ir.TextOut.Op.{Print, Println, Report, Debug, Finish}
   end Op
 
   object Ops:
     def debug(args: DFValAny*)(using DFC): Unit =
       TextOut(Op.Debug, Nil, args.toList)
 
+    def finish()(using DFC): Unit =
+      TextOut(Op.Finish, Nil, Nil)
+
     transparent inline def print(inline msg: Any): Unit =
       compiletime.summonFrom {
         case given DomainType =>