fix verilog.v95/v2001 default parameters issues and remove wrong verilator linting suppression

Author: Oron Port

compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogOwnerPrinter.scala

@@ -23,6 +23,10 @@ protected trait VerilogOwnerPrinter extends AbstractOwnerPrinter:
     printer.dialect match
       case VerilogDialect.v95 => false
       case _                  => true
+  val noDefaultParamSupport: Boolean =
+    printer.dialect match
+      case VerilogDialect.v95 | VerilogDialect.v2001 => false
+      case _                                         => true
   def csModuleDcl(design: DFDesignBlock): String =
     val designMembers = design.members(MemberView.Folded)
     val ports = designMembers.view.collect { case p @ DclPort() =>
@@ -71,7 +75,18 @@ protected trait VerilogOwnerPrinter extends AbstractOwnerPrinter:
       }
     )
     val designParamList = designMembers.collect { case param: DesignParam =>
-      val defaultValue = if (design.isTop) s" = ${param.dfValRef.refCodeString}" else ""
+      val defaultValue =
+        if (design.isTop) s" = ${param.dfValRef.refCodeString}"
+        else
+          param.defaultRef.get match
+            case DFMember.Empty =>
+              // missing default values are supported
+              if (noDefaultParamSupport) ""
+              // missing default values are not supported, so we fetch a valid constant data
+              // (different instances may have different constant data, but for default,
+              // a single module description can have any valid data, just to satisfy the standard)
+              else s" = ${printer.csConstData(param.dfType, param.getConstData.get)}"
+            case _ => s" = ${param.defaultRef.refCodeString}"
       s"parameter ${printer.csDFType(param.dfType)} ${param.getName}$defaultValue"
     }
     val designParamCS =

compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogValPrinter.scala

@@ -19,7 +19,17 @@ protected trait VerilogValPrinter extends AbstractValPrinter:
     if (supportGlobalParameters || !dfVal.isGlobal)
       val arrRange = printer.csDFVectorRanges(dfVal.dfType)
       val endOfStatement = if (dfVal.isGlobal) ";" else ""
-      s"parameter ${printer.csDFType(dfVal.dfType).emptyOr(_ + " ")}${dfVal.getName}${arrRange} = ${csDFValExpr(dfVal)}$endOfStatement"
+      val default = dfVal match
+        // for non-top-level design parameters, we fetch the default value if it is defined.
+        // for all other cases, we get the parameter constant data and use that as default value.
+        // using the constant data only happens in verilog.v95, since parameters are declared in
+        // the body and must have defaults.
+        case param: DesignParam =>
+          param.defaultRef.get match
+            case defaultVal: CanBeExpr if !param.getOwnerDesign.isTop => csDFValExpr(defaultVal)
+            case _ => printer.csConstData(param.dfType, param.getConstData.get)
+        case _ => csDFValExpr(dfVal)
+      s"parameter ${printer.csDFType(dfVal.dfType).emptyOr(_ + " ")}${dfVal.getName}${arrRange} = $default$endOfStatement"
     else s"`define ${dfVal.getName} ${csDFValExpr(dfVal).replace("\n", " \\\n")}"
 
   def csDFValDclWithoutInit(dfVal: Dcl): String =

compiler/stages/src/test/scala/StagesSpec/PrintVerilogCodeSpec.scala

@@ -106,12 +106,12 @@ class PrintVerilogCodeSpec extends StageSpec:
   }
 
   test("Basic hierarchy design with parameters") {
-    class ID(val width: Int <> CONST) extends DFDesign:
+    class ID(val width: Int <> CONST = 7) extends DFDesign:
       val x = SInt(width) <> IN
       val y = SInt(width) <> OUT
       y := x
 
-    class IDTop(val width: Int <> CONST) extends DFDesign:
+    class IDTop(val width: Int <> CONST = 9) extends DFDesign:
       val x   = SInt(width) <> IN
       val y   = SInt(width) <> OUT
       val id1 = ID(width)
@@ -126,7 +126,7 @@ class PrintVerilogCodeSpec extends StageSpec:
          |`timescale 1ns/1ps
          |`include "IDTop_defs.svh"
          |
-         |module ID#(parameter int width)(
+         |module ID#(parameter int width = 7)(
          |  input  wire logic signed [width - 1:0] x,
          |  output logic signed [width - 1:0] y
          |);
@@ -169,12 +169,12 @@ class PrintVerilogCodeSpec extends StageSpec:
 
   test("Basic hierarchy design with parameters verilog.v95") {
     given options.CompilerOptions.Backend = backends.verilog.v95
-    class ID(val width: Int <> CONST) extends DFDesign:
+    class ID(val width: Int <> CONST = 7) extends DFDesign:
       val x = SInt(width) <> IN
       val y = SInt(width) <> OUT
       y := x
 
-    class IDTop(val width: Int <> CONST) extends DFDesign:
+    class IDTop(val width: Int <> CONST = 9) extends DFDesign:
       val x   = SInt(width) <> IN
       val y   = SInt(width) <> OUT
       val id1 = ID(width)
@@ -194,7 +194,7 @@ class PrintVerilogCodeSpec extends StageSpec:
          |  y
          |);
          |  `include "dfhdl_defs.vh"
-         |  parameter integer width = width;
+         |  parameter integer width = 7;
          |  input  wire  [width - 1:0] x;
          |  output wire [width - 1:0] y;
          |  assign y = x;

lib/src/main/scala/dfhdl/tools/toolsCore/Verilator.scala

@@ -82,8 +82,7 @@ class VerilatorConfigPrinter(verilatorVersion: String)(using
        |$commands
        |""".stripMargin
   def commands: String =
-    lintOffUninitializedParams.emptyOr(_ + "\n") +
-      lintOffHidden.emptyOr(_ + "\n") +
+    lintOffHidden.emptyOr(_ + "\n") +
       lintOffBlackBoxes.emptyOr(_ + "\n") +
       lintOffOpenOutPorts.emptyOr(_ + "\n") +
       lintOffUnused.emptyOr(_ + "\n") +
@@ -101,12 +100,6 @@ class VerilatorConfigPrinter(verilatorVersion: String)(using
     val lineArg = lines.emptyOr(" -lines " + _)
     val matchWildArg = matchWild.emptyOr(m => s""" -match "$m"""")
     s"lint_off$ruleArg$fileArg$lineArg$matchWildArg"
-  def lintOffUninitializedParams: String =
-    lintOffCommand(
-      rule = "NEWERSTD",
-      file = "*.*",
-      matchWild = "*Parameter requires default value*"
-    )
   def lintOffHidden: String = lintOffCommand("VARHIDDEN")
   def lintOffBlackBoxes: String =
     designDB.srcFiles.flatMap {

lib/src/test/resources/ref/AES.CipherSpecNoOpaques/verilog.v2001/hdl/mulByte_0.v

@@ -2,7 +2,7 @@
 `timescale 1ns/1ps
 `include "CipherNoOpaques_defs.vh"
 
-module mulByte_0#(parameter logic [7:0] lhs)(
+module mulByte_0#(parameter logic [7:0] lhs = 8'h02)(
   input  wire  [7:0] rhs,
   output wire [7:0]  o
 );

lib/src/test/resources/ref/AES.CipherSpecNoOpaques/verilog.v2001/hdl/mulByte_1.v

@@ -2,7 +2,7 @@
 `timescale 1ns/1ps
 `include "CipherNoOpaques_defs.vh"
 
-module mulByte_1#(parameter logic [7:0] lhs)(
+module mulByte_1#(parameter logic [7:0] lhs = 8'h03)(
   input  wire  [7:0] rhs,
   output wire [7:0]  o
 );

lib/src/test/resources/ref/AES.CipherSpecNoOpaques/verilog.v2001/hdl/mulByte_2.v

@@ -2,7 +2,7 @@
 `timescale 1ns/1ps
 `include "CipherNoOpaques_defs.vh"
 
-module mulByte_2#(parameter logic [7:0] lhs)(
+module mulByte_2#(parameter logic [7:0] lhs = 8'h01)(
   input  wire  [7:0] rhs,
   output wire [7:0]  o
 );

lib/src/test/resources/ref/AES.CipherSpecWithOpaques/verilog.v2001/hdl/mulByte_0.v

@@ -2,7 +2,7 @@
 `timescale 1ns/1ps
 `include "Cipher_defs.vh"
 
-module mulByte_0#(parameter logic [7:0] lhs)(
+module mulByte_0#(parameter logic [7:0] lhs = 8'h02)(
   input  wire  [7:0] rhs,
   output wire [7:0]  o
 );

lib/src/test/resources/ref/AES.CipherSpecWithOpaques/verilog.v2001/hdl/mulByte_1.v

@@ -2,7 +2,7 @@
 `timescale 1ns/1ps
 `include "Cipher_defs.vh"
 
-module mulByte_1#(parameter logic [7:0] lhs)(
+module mulByte_1#(parameter logic [7:0] lhs = 8'h03)(
   input  wire  [7:0] rhs,
   output wire [7:0]  o
 );

lib/src/test/resources/ref/AES.CipherSpecWithOpaques/verilog.v2001/hdl/mulByte_2.v

@@ -2,7 +2,7 @@
 `timescale 1ns/1ps
 `include "Cipher_defs.vh"
 
-module mulByte_2#(parameter logic [7:0] lhs)(
+module mulByte_2#(parameter logic [7:0] lhs = 8'h01)(
   input  wire  [7:0] rhs,
   output wire [7:0]  o
 );