tools refactoring and verilator simulation support

Author: Oron Port

compiler/ir/src/main/scala/dfhdl/compiler/ir/SourceFile.scala

@@ -14,7 +14,7 @@ object SourceType:
     case BlackBox
     case GlobalDef
     case DFHDLDef
-  trait ToolConfig extends SourceType
+  trait Tool extends SourceType
 
 enum SourceOrigin derives CanEqual:
   // Compiled files are a result from a compilation process.

lib/src/main/scala/dfhdl/default.scala

@@ -12,8 +12,8 @@ extension [D <: Design](cd: CompiledDesign[D])
       lo: LinterOptions
   ): CompiledDesign[D] =
     co.backend match
-      case _: backends.verilog => lo.verilogLinter.lint(lo.verilogLinter.preprocess(cd))
-      case _: backends.vhdl    => lo.vhdlLinter.lint(lo.vhdlLinter.preprocess(cd))
+      case _: backends.verilog => lo.verilogLinter.lint(lo.verilogLinter.lintPreprocess(cd))
+      case _: backends.vhdl    => lo.vhdlLinter.lint(lo.vhdlLinter.lintPreprocess(cd))
   def simulate(using
       co: CompilerOptions,
       so: SimulatorOptions
@@ -22,13 +22,15 @@ extension [D <: Design](cd: CompiledDesign[D])
     import stagedDB.getSet
     if (stagedDB.inSimulation)
       co.backend match
-        case _: backends.verilog => so.verilogSimulator.simulate(so.verilogSimulator.preprocess(cd))
-        case _: backends.vhdl    => so.vhdlSimulator.simulate(so.vhdlSimulator.preprocess(cd))
+        case _: backends.verilog =>
+          so.verilogSimulator.simulate(so.verilogSimulator.simulatePreprocess(cd))
+        case _: backends.vhdl => so.vhdlSimulator.simulate(so.vhdlSimulator.simulatePreprocess(cd))
     else
       throw new Exception(
         s"The top design `${stagedDB.top.getName}` has ports and therefore cannot be simulated."
       )
+  end simulate
 
   def build(using builder: Builder)(using CompilerOptions, BuilderOptions): CompiledDesign[D] =
-    builder.build(builder.preprocess(cd))
+    builder.build(builder.buildPreprocess(cd))
 end extension

lib/src/main/scala/dfhdl/tools/toolsCore/Tool.scala

@@ -18,10 +18,6 @@ trait Tool:
     if (osName.contains("windows")) windowsBinExec else binExec
   protected def binExec: String
   protected def windowsBinExec: String = s"$binExec.exe"
-  protected[dfhdl] def preprocess[D <: Design](cd: CompiledDesign[D])(using
-      CompilerOptions,
-      ToolOptions
-  ): CompiledDesign[D] = cd
   final protected def addSourceFiles[D <: Design](
       cd: CompiledDesign[D],
       sourceFiles: List[SourceFile]
@@ -173,6 +169,10 @@ trait VerilogTool extends Tool:
 trait VHDLTool extends Tool
 
 trait Linter extends Tool:
+  protected[dfhdl] def lintPreprocess[D <: Design](cd: CompiledDesign[D])(using
+      CompilerOptions,
+      ToolOptions
+  ): CompiledDesign[D] = cd
   final def lint[D <: Design](
       cd: CompiledDesign[D]
   )(using CompilerOptions, ToolOptions): CompiledDesign[D] =
@@ -211,9 +211,13 @@ trait VHDLLinter extends Linter, VHDLTool:
     lintCmdLanguageFlag(co.backend.asInstanceOf[dfhdl.backends.vhdl].dialect)
 
 trait Simulator extends Tool:
+  protected[dfhdl] def simulatePreprocess[D <: Design](cd: CompiledDesign[D])(using
+      CompilerOptions,
+      SimulatorOptions
+  ): CompiledDesign[D] = cd
   val simRunsLint: Boolean = false
   protected def simRunExec: String = this.runExec
-  final def simulate[D <: Design](
+  def simulate[D <: Design](
       cd: CompiledDesign[D]
   )(using CompilerOptions, SimulatorOptions): CompiledDesign[D] =
     given MemberGetSet = cd.stagedDB.getSet
@@ -279,6 +283,10 @@ trait VHDLSimulator extends Simulator, VHDLTool:
     simulateCmdLanguageFlag(co.backend.asInstanceOf[dfhdl.backends.vhdl].dialect)
 
 trait Builder extends Tool:
+  protected[dfhdl] def buildPreprocess[D <: Design](cd: CompiledDesign[D])(using
+      CompilerOptions,
+      BuilderOptions
+  ): CompiledDesign[D] = cd
   def build[D <: Design](
       cd: CompiledDesign[D]
   )(using CompilerOptions, BuilderOptions): CompiledDesign[D]

lib/src/main/scala/dfhdl/tools/toolsCore/Verilator.scala

@@ -26,7 +26,7 @@ object Verilator extends VerilogLinter, VerilogSimulator:
 
   override protected def toolFiles(using getSet: MemberGetSet): List[String] =
     getSet.designDB.srcFiles.collect {
-      case SourceFile(SourceOrigin.Committed, VerilatorConfig, path, _) =>
+      case SourceFile(SourceOrigin.Committed, _: VerilatorToolSource, path, _) =>
         path.convertWindowsToLinuxPaths
     }
 
@@ -52,8 +52,10 @@ object Verilator extends VerilogLinter, VerilogSimulator:
     constructCommand(
       "--lint-only",
       "--quiet-stats",
+      s"--top-module ${topName}",
       if (hasTiming) "--timing" else ""
     )
+  end lintCmdPreLangFlags
 
   override protected def lintCmdPostLangFlags(using
       CompilerOptions,
@@ -64,17 +66,56 @@ object Verilator extends VerilogLinter, VerilogSimulator:
     (!summon[LinterOptions].Werror.toBoolean).toFlag("-Wno-fatal")
   )
 
-  override protected[dfhdl] def preprocess[D <: Design](cd: CompiledDesign[D])(using
+  override protected def simulateCmdPreLangFlags(using
+      CompilerOptions,
+      SimulatorOptions,
+      MemberGetSet
+  ): String =
+    constructCommand(
+      "--binary",
+      "--quiet-stats",
+      s"--top-module ${topName}"
+    )
+
+  override protected[dfhdl] def lintPreprocess[D <: Design](cd: CompiledDesign[D])(using
       CompilerOptions,
       ToolOptions
   ): CompiledDesign[D] =
     addSourceFiles(
       cd,
       List(new VerilatorConfigPrinter(getInstalledVersion)(using cd.stagedDB.getSet).getSourceFile)
     )
+
+  // override protected[dfhdl] def simulatePreprocess[D <: Design](cd: CompiledDesign[D])(using
+  //     CompilerOptions,
+  //     SimulatorOptions
+  // ): CompiledDesign[D] =
+  //   addSourceFiles(
+  //     cd,
+  //     List(new VerilatorSimMainPrinter(getInstalledVersion)(using cd.stagedDB.getSet).getSourceFile)
+  //   )
+
+  override protected def simulateCmdLanguageFlag(dialect: VerilogDialect): String =
+    lintCmdLanguageFlag(dialect)
+
+  override def simulate[D <: Design](
+      cd: CompiledDesign[D]
+  )(using CompilerOptions, SimulatorOptions): CompiledDesign[D] =
+    val ret = super.simulate(cd)
+    given MemberGetSet = ret.stagedDB.getSet
+    val unixExec =
+      s"${Paths.get(execPath).toAbsolutePath()}${separatorChar}obj_dir${separatorChar}V${topName}"
+    val runExec: String =
+      val osName: String = sys.props("os.name").toLowerCase
+      if (osName.contains("windows")) s"${unixExec}.exe" else unixExec
+    exec(cmd = "", runExec = runExec)
+    ret
+
 end Verilator
 
-case object VerilatorConfig extends SourceType.ToolConfig
+sealed trait VerilatorToolSource extends SourceType.Tool
+
+case object VerilatorConfig extends VerilatorToolSource
 
 class VerilatorConfigPrinter(verilatorVersion: String)(using
     getSet: MemberGetSet,
@@ -171,3 +212,48 @@ class VerilatorConfigPrinter(verilatorVersion: String)(using
     SourceFile(SourceOrigin.Compiled, VerilatorConfig, configFileName, contents)
 
 end VerilatorConfigPrinter
+
+case object VerilatorSimMain extends VerilatorToolSource
+
+// class VerilatorSimMainPrinter(verilatorVersion: String)(using
+//     getSet: MemberGetSet,
+//     co: CompilerOptions,
+//     so: SimulatorOptions
+// ):
+//   val designDB: DB = getSet.designDB
+//   val topName = designDB.top.dclName
+//   def mainFileName: String = s"${topName}.cpp"
+//   def contents: String =
+//     s"""|#include "V${topName}.h"
+//         |#include "verilated.h"
+//         |#include "V${topName}___024root.h"
+//         |
+//         |int main(int argc, char** argv) {
+//         |    // Initialize Verilator
+//         |    Verilated::commandArgs(argc, argv);
+//         |
+//         |    // Create instance of our module
+//         |    V${topName}* top = new V${topName};
+//         |
+//         |    // Initialize simulation inputs
+//         |    V${topName}___024root* rootp = top->rootp;
+//         |    rootp->${topName}__DOT__rst = 1;
+//         |
+//         |    while (!Verilated::gotFinish()) {
+//         |        // Toggle clock
+//         |        rootp->${topName}__DOT__clk = 0;
+//         |        top->eval();
+//         |        rootp->${topName}__DOT__clk = 1;
+//         |        top->eval();
+//         |        rootp->${topName}__DOT__rst = 0;
+//         |    }
+//         |
+//         |    // Cleanup
+//         |    delete top;
+//         |
+//         |    return 0;
+//         |}
+//         |""".stripMargin
+//   def getSourceFile: SourceFile =
+//     SourceFile(SourceOrigin.Compiled, VerilatorSimMain, mainFileName, contents)
+// end VerilatorSimMainPrinter

lib/src/main/scala/dfhdl/tools/toolsCore/Vivado.scala

@@ -19,9 +19,9 @@ object Vivado extends Builder:
     versionPattern.findFirstMatchIn(cmdRetStr).map(_.group(1))
 
   def filesCmdPart[D <: Design](cd: CompiledDesign[D]): String = ???
-  override protected[dfhdl] def preprocess[D <: Design](cd: CompiledDesign[D])(using
+  override protected[dfhdl] def buildPreprocess[D <: Design](cd: CompiledDesign[D])(using
       CompilerOptions,
-      ToolOptions
+      BuilderOptions
   ): CompiledDesign[D] =
     addSourceFiles(
       cd,
@@ -37,7 +37,7 @@ object Vivado extends Builder:
     cd
 end Vivado
 
-case object VivadoProjectTclConfig extends SourceType.ToolConfig
+case object VivadoProjectTclConfig extends SourceType.Tool
 
 class VivadoProjectTclConfigPrinter(using getSet: MemberGetSet):
   val designDB: DB = getSet.designDB