Skip to content

Commit e160ade

Browse files
author
Oron Port
committed
trap runtime warnings in verilator simulations for non-zero exit code under Werror-tool
1 parent 7a1d727 commit e160ade

File tree

1 file changed

+21
-3
lines changed

1 file changed

+21
-3
lines changed

lib/src/main/scala/dfhdl/tools/toolsCore/Verilator.scala

Lines changed: 21 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,15 @@ object Verilator extends VerilogLinter, VerilogSimulator:
7878
s"--top-module ${topName}"
7979
)
8080

81+
override protected def simulateCmdPostLangFlags(using
82+
CompilerOptions,
83+
SimulatorOptions,
84+
MemberGetSet
85+
): String = constructCommand(
86+
"-Wall",
87+
(!summon[LinterOptions].Werror.toBoolean).toFlag("-Wno-fatal")
88+
)
89+
8190
override protected[dfhdl] def lintPreprocess[D <: Design](cd: CompiledDesign[D])(using
8291
CompilerOptions,
8392
ToolOptions
@@ -135,7 +144,7 @@ object Verilator extends VerilogLinter, VerilogSimulator:
135144
// Print progress percentage
136145
if (totalCompilations > 0)
137146
val percentage = (cpps * 100) / totalCompilations
138-
print(s"\rCompiling Verilated C++ files: $percentage%")
147+
print(s"\rCompiling verilated C++ files: $percentage%")
139148
if (cpps >= totalCompilations)
140149
println() // Add a newline when complete
141150
totalCompilations = 0
@@ -147,7 +156,7 @@ object Verilator extends VerilogLinter, VerilogSimulator:
147156

148157
override def simulate[D <: Design](
149158
cd: CompiledDesign[D]
150-
)(using CompilerOptions, SimulatorOptions): CompiledDesign[D] =
159+
)(using co: CompilerOptions, so: SimulatorOptions): CompiledDesign[D] =
151160
val ret = super.simulate(cd)
152161
given MemberGetSet = ret.stagedDB.getSet
153162
val unixExec =
@@ -156,8 +165,17 @@ object Verilator extends VerilogLinter, VerilogSimulator:
156165
val osName: String = sys.props("os.name").toLowerCase
157166
if (osName.contains("windows")) s"${unixExec}.exe" else unixExec
158167
println("Executing verilated binary...")
159-
exec(cmd = "", runExec = runExec)
168+
// set special logger to identify warnings, because verilator does not track warnings.
169+
val logger = Some(
170+
Tool.ProcessLogger(
171+
// `WARNING:` is used by DFHDL when compiling to v95/v2001 dialects
172+
lineIsWarning = (line: String) => line.startsWith("WARNING:") || line.contains("%Warning:"),
173+
lineIsSuppressed = (line: String) => false
174+
)
175+
)
176+
exec(cmd = "", loggerOpt = logger, runExec = runExec)
160177
ret
178+
end simulate
161179

162180
end Verilator
163181

0 commit comments

Comments
 (0)