@@ -78,6 +78,15 @@ object Verilator extends VerilogLinter, VerilogSimulator:
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s " --top-module ${topName}"
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)
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+ override protected def simulateCmdPostLangFlags (using
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+ CompilerOptions ,
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+ SimulatorOptions ,
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+ MemberGetSet
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+ ): String = constructCommand(
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+ " -Wall" ,
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+ (! summon[LinterOptions ].Werror .toBoolean).toFlag(" -Wno-fatal" )
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+ )
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+
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override protected [dfhdl] def lintPreprocess [D <: Design ](cd : CompiledDesign [D ])(using
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CompilerOptions ,
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ToolOptions
@@ -135,7 +144,7 @@ object Verilator extends VerilogLinter, VerilogSimulator:
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// Print progress percentage
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if (totalCompilations > 0 )
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val percentage = (cpps * 100 ) / totalCompilations
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- print(s " \r Compiling Verilated C++ files: $percentage% " )
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+ print(s " \r Compiling verilated C++ files: $percentage% " )
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if (cpps >= totalCompilations)
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println() // Add a newline when complete
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totalCompilations = 0
@@ -147,7 +156,7 @@ object Verilator extends VerilogLinter, VerilogSimulator:
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override def simulate [D <: Design ](
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cd : CompiledDesign [D ]
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- )(using CompilerOptions , SimulatorOptions ): CompiledDesign [D ] =
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+ )(using co : CompilerOptions , so : SimulatorOptions ): CompiledDesign [D ] =
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val ret = super .simulate(cd)
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given MemberGetSet = ret.stagedDB.getSet
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val unixExec =
@@ -156,8 +165,17 @@ object Verilator extends VerilogLinter, VerilogSimulator:
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val osName : String = sys.props(" os.name" ).toLowerCase
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if (osName.contains(" windows" )) s " ${unixExec}.exe " else unixExec
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println(" Executing verilated binary..." )
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- exec(cmd = " " , runExec = runExec)
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+ // set special logger to identify warnings, because verilator does not track warnings.
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+ val logger = Some (
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+ Tool .ProcessLogger (
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+ // `WARNING:` is used by DFHDL when compiling to v95/v2001 dialects
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+ lineIsWarning = (line : String ) => line.startsWith(" WARNING:" ) || line.contains(" %Warning:" ),
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+ lineIsSuppressed = (line : String ) => false
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+ )
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+ )
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+ exec(cmd = " " , loggerOpt = logger, runExec = runExec)
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ret
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+ end simulate
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end Verilator
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