add finish as a verilog keyword to color

Oron Port · Oron Port · commit fd87fc0be8dc · 2025-05-15T00:32:18.000+03:00
diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogPrinter.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/verilog/VerilogPrinter.scala
@@ -236,7 +236,7 @@ class VerilogPrinter(val dialect: VerilogDialect)(using
     "begin", "end", "case", "default", "endcase", "default_nettype", "include", "inside",
     "timescale", "if", "else", "typedef", "enum", "posedge", "negedge", "assign", "parameter",
     "struct", "packed", "ifndef", "endif", "define", "function", "endfunction", "for", "while",
-    "assert", "write", "display", "info", "warning", "error", "fatal"
+    "assert", "write", "display", "info", "warning", "error", "fatal", "finish"
   )
   val verilogOps: Set[String] = Set("=", "<=")
   val verilogTypes: Set[String] = Set(

Original file line number	Diff line number	Diff line change
`@@ -236,7 +236,7 @@ class VerilogPrinter(val dialect: VerilogDialect)(using`
`236`	`236`	`"begin", "end", "case", "default", "endcase", "default_nettype", "include", "inside",`
`237`	`237`	`"timescale", "if", "else", "typedef", "enum", "posedge", "negedge", "assign", "parameter",`
`238`	`238`	`"struct", "packed", "ifndef", "endif", "define", "function", "endfunction", "for", "while",`
`239`		`- "assert", "write", "display", "info", "warning", "error", "fatal"`
	`239`	`+ "assert", "write", "display", "info", "warning", "error", "fatal", "finish"`
`240`	`240`	`)`
`241`	`241`	`val verilogOps: Set[String] = Set("=", "<=")`
`242`	`242`	`val verilogTypes: Set[String] = Set(`